EDBT 2026 Demo / reviewers in the wild / expert
Y. Mukai
dblp:173/1855
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 1974
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 50% Hardware reliability and fault tolerance · 25% Integrated circuit design · 25% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design › digital circuit design › sequential circuit design
asynchronous sequential circuits |
0.0 | 1 | 1974 | A Method for the Realization of Fail-Safe Asynchronous Sequential Circuits · IEEE Trans. Computers 1974 |
Hardware reliability and fault tolerance › design for reliability
fail-safe circuit design |
0.0 | 1 | 1974 | A Method for the Realization of Fail-Safe Asynchronous Sequential Circuits · IEEE Trans. Computers 1974 |
Electronic design automation
logic synthesis |
0.0 | 1 | 1974 | A Method for the Realization of Fail-Safe Asynchronous Sequential Circuits · IEEE Trans. Computers 1974 |
Electronic design automation › logic synthesis
state assignment |
0.0 | 1 | 1974 | A Method for the Realization of Fail-Safe Asynchronous Sequential Circuits · IEEE Trans. Computers 1974 |
Methods — techniques the papers use, named apart from their topics
tracey's method · 0.0ordered partition · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1974 | A Method for the Realization of Fail-Safe Asynchronous Sequential CircuitsabstractThe problem of the realization of fail-safe asynchronous sequential circuits was recently studied by Patterson and Sawin. This correspondence presents a different approach to the same subject which, in some cases, yield us simpler realization than those by the methods ever proposed, combining the notion of the ordered partition with Tracey's method for the state assignment of asynchronous sequential circuit. Y. Mukai, Yoshihiro Tohma |
IEEE Trans. Computers | 1 |