EDBT 2026 Demo / reviewers in the wild / expert
Andy Anderson
dblp:173/5694
· DBLP profile ↗
3ranked-venue papers
0as first author
3since 2021 · last 2025
0009-0004-6022-8098ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Memory systems · 49% Cloud and datacenter computing · 28% Hardware accelerators and domain-specific architectures · 14% | |
| Software engineering, system software, and programming languages
2 papers |
Operating systems · 100% |
Topics — the 9 heaviest of 12, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems › memory management › virtual memory
address translation |
0.9 | 1 | 2025 | Learning to Walk: Architecting Learned Virtual Memory Translation · MICRO 2025 |
Memory systems › memory management › virtual memory
page table |
0.9 | 1 | 2025 | Learning to Walk: Architecting Learned Virtual Memory Translation · MICRO 2025 |
Memory systems › memory management
virtual memory |
0.9 | 1 | 2025 | Learning to Walk: Architecting Learned Virtual Memory Translation · MICRO 2025 |
Operating systems › resource management › process management
CPU scheduling |
0.8 | 1 | 2024 | LibPreemptible: Enabling Fast, Adaptive, and Hardware-Assisted User-Space Scheduling · HPCA 2024 |
Operating systems › resource management › process management › CPU scheduling
user-space scheduling |
0.8 | 1 | 2024 | LibPreemptible: Enabling Fast, Adaptive, and Hardware-Assisted User-Space Scheduling · HPCA 2024 |
Hardware accelerators and domain-specific architectures › domain-specific accelerator
compression accelerator |
0.8 | 1 | 2024 | Sabre: Hardware-Accelerated Snapshot Compression for Serverless MicroVMs · OSDI 2024 |
Cloud and datacenter computing
serverless computing |
0.8 | 1 | 2024 | Sabre: Hardware-Accelerated Snapshot Compression for Serverless MicroVMs · OSDI 2024 |
Operating systems › resource management
memory management |
0.3 | 1 | 2025 | Learning to Walk: Architecting Learned Virtual Memory Translation · MICRO 2025 |
Parallel and multicore computing › parallel scheduling
thread scheduling |
0.2 | 1 | 2024 | LibPreemptible: Enabling Fast, Adaptive, and Hardware-Assisted User-Space Scheduling · HPCA 2024 |
Methods — techniques the papers use, named apart from their topics
learned index · 1.7fixed-point arithmetic · 1.7RTL synthesis · 1.7hardware-assisted interrupts · 1.5adaptive scheduling policies · 1.5hardware acceleration · 0.8
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | Learning to Walk: Architecting Learned Virtual Memory TranslationabstractThe rise in memory demands of emerging datacenter applications has placed virtual memory translation in the spotlight, exposing it as a significant performance bottleneck.To address this problem, this paper introduces Learned Virtual Memory (LVM), a page table structure that effectively provides optimal single-access address translation.LVM is founded on a novel learned index model that dynamically adapts the address translation procedure based on the characteristics of an application's virtual address space.Furthermore, LVM's learned index requires minimal memory space, does not impose stringent physical contiguity requirements, enjoys high cacheability in the MMU, efficiently supports insertions, and relies on simple fixed-point arithmetic.Finally, LVM supports all features of virtual memory, including multiple page sizes.We evaluate LVM with a set of operating system (OS) extensions in Linux, RTL synthesis, and full-system simulations across a wide range of workloads.LVM reduces the address translation overhead by an average of 44% over radix page tables, while reducing the page walk cache area required by 1.5×.Overall, LVM achieves a 2-27% speedup in application execution time and is within 1% of an ideal page table. Kaiyang Zhao 0002, Xenia Xu, Dan Schatzberg, Nastaran Hajinaza, Rupin Vakharwala, Andy Anderson, Dimitrios Skarlatos 0002 |
MICRO | 7 |
| 2024 | LibPreemptible: Enabling Fast, Adaptive, and Hardware-Assisted User-Space SchedulingabstractModern cloud applications are prone to high tail latencies since their requests typically follow highly-dispersive distributions. Prior work has proposed both OS- and systemlevel solutions to reduce tail latencies for microsecond-scale workloads through better scheduling. Unfortunately, existing approaches like customized dataplane OSes, require significant OS changes, experience scalability limitations, or do not reach the full performance capabilities hardware offers. We propose LibPreemptible, a preemptive user-level threading library that is flexible, lightweight, and scalable. LibPreemptible is based on three key techniques: 1) a fast and lightweight hardware mechanism for delivery of timed interrupts, 2) a general-purpose user-level scheduling interface, and 3) an API for users to express adaptive scheduling policies tailored to the needs of their applications. Compared to the prior state-of-the-art scheduling system Shinjuku, our system achieves significant tail latency and throughput improvements for various workloads without the need to modify the kernel. We also demonstrate the flexibility of LibPreemptible across scheduling policies for real applications experiencing varying load levels and characteristics. Nikita Lazarev, David Koufaty, Tenny Yin, Andy Anderson, Zhiru Zhang, G. Edward Suh, Kostis Kaffes, Christina Delimitrou |
HPCA | 5 |
| 2024 | Sabre: Hardware-Accelerated Snapshot Compression for Serverless MicroVMs
Nikita Lazarev, Varun Gohil, James Tsai, Andy Anderson, Bhushan Chitlur, Zhiru Zhang, Christina Delimitrou |
OSDI | 4 |