Timing behavior of standard cells is represented as two-dimensional tables in a timing library, where each table entry is obtained through transistor-level simulation. As technology scales, the number of design corners and standard cells has increased dramatically, leading to a substantial increase in simulation time for timing characterization. This may delay the design schedule or impose additional demands on tool licenses. To address this challenge, we propose a fast timing characterization method that selectively uses transistor-level simulation and model-based prediction. In this method, a subset of table entries is obtained through simulation, while the remaining entries are predicted by regression models trained on the simulated data. Multiple regression models are employed to capture the diverse characteristics of each entry location, and the most accurate model for each entry is identified at one corner, called an anchor corner. The selected models are then used to predict the corresponding entry at target corners. Experimental results show that the proposed method achieves high accuracy with a 40% reduction in runtime; the mean and 3-sigma absolute errors are 0.4% and 2.3%, respectively, representing a significant improvement over conventional methods. The accuracy of the proposed method is further validated on 7-nm technology libraries.

Multiple threshold voltage (multi-Vth) optimization reduces leakage by replacing low-Vth cells with high-Vth cells but is limited by tight design constraints and timing violations on critical paths. This paper proposes a novel approach using mixed-Vth cells, where pull-up and pull-down networks are independently optimized for different Vth types. By selectively assigning higher Vth to only one of the networks, the proposed method achieves significant leakage reduction without violating timing constraints. The methodology ensures to satisfy the constraint of minimum implant width through localized cell relocation. Experimental results show a reduction in leakage power by 22% on average with no timing violation in practical runtime, while the conventional cell-based method reduces 10% of leakage.

IR-drop analysis of analog circuits is a challenge because the current waveforms of target transistors, with connection to VDD or VSS, are extracted through transistor-level simulation, and the analysis itself, in particular dynamic one, is computationally expensive. We introduce two ML models for high-speed analysis. (1) Recurrent synchronized graph convolutional network (RS-GCN) is used for quick prediction of current waveforms. Each subcircuit is modeled with recurrent-GCN, in which recurrent connection is for the analysis in discrete time series. Recurrent-GCNs are synchronized to take account of common connections including VDD, VSS, and the inputs and outputs of subcircuits. Experiments show that RS-GCN takes only 0.85% of SPICE runtime, while prediction error is 14% on average. (2) Y-Net is applied for actual IR-drop analysis of small layout partition, one by one. Pad location and PDN resistance are provided as one 2D input of Y-Net; they are encoded and go through GCNs to account for neighbor layout partitions. Current map, derived from RS-GCN, becomes the second input. Final IR-drop map is extracted from the decoder. Experiments demonstrate that Y-Net, in conjunction with RS-GCN for current extraction, takes 2.5% of runtime from popular commercial solution with 15% prediction inaccuracy.

Interpolation is used to approximate the timing parameters of logic cells not specified in timing tables. Bilinear interpolation has been taken for granted in the industry, but the error increases as the nonlinearity of the timing parameters increases. In this article, we propose machine learning (ML)-based interpolation to obtain more accurate timing parameters. Recurrent convolutional neural network (R-CNN) is employed and various ranges of table entries form a sequence of input data, in which the recurrent network allows them to influence the interpolation. In addition, variational autoencoder (VAE) is used to capture the distribution feature of the table. ML interpolation is parallelized in GPU to minimize the runtime overhead from numerous arithmetic operations. Experimental results demonstrate that ML interpolation reduces timing parameter error by 19.7% and path delay error by 3.4% compared to bilinear interpolation at the cost of 13% runtime overhead.

Decoupling capacitor (decap) cells are inserted near function cells of high switching activities so that their IR-drop can be suppressed. Decaps become more complex these days while a number of metal layers are used for internal connection, thereby starting to manifest themselves as routing blockage. Postplacement decap insertion with both IR-drop violations and routing design rule violations (DRVs) being taken into account is addressed for the first time. Local cell relocation is performed to reduce the number of decaps in the actual decap insertion step. U-Net integrated with a graph convolutional network (GCN) is introduced to predict the DRV probability, which drives decap insertion. The problem of decap insertion is then formulated as mixed integer quadratically constrained programming (MIQCP) and a heuristic algorithm is presented for practical application. Experiments with a few test circuits demonstrate that the increase in routing DRV is reduced by 26% on average with no IR-drop violations, compared to conventional methods that do not explicitly consider DRVs. This brings a 60% reduction in routing runtime and a 33% improvement in total negative slack (TNS).

Decoupling capacitor (decap) cells are inserted near function cells of high switching activities so that their IR-drop can be suppressed. Their design becomes more complex and uses higher metal layers, thereby starting to manifest themselves as routing blockage. Post-placement decap insertion, with a goal of minimizing both IR-drop violations and routing design rule violations (DRVs), is addressed for the first time. U-Net with graph convolutional network is introduced to predict routing DRV penalty. The decap insertion problem is formulated and a heuristic algorithm is presented. Experiments with a few test circuits demonstrate that DRVs are reduced by 16% on average with no IR-drop violations, compared to a conventional method which does not explicitly consider DRVs. This results in 48% reduction in routing runtime and 23% improvement in total negative slack.

Power distribution network (PDN) consumes many routing resources to satisfy IR-drop constraints. With the increasing IR drop and the decreasing metal tracks in recent technology, the design of PDN becomes very important for circuit routing. In this paper, post-placement PDN optimization is proposed for routability enhancement. For a given regular PDN, we iteratively remove partial straps that have a small impact on IR-drop while improving routing overflow. Hierarchical layout-aware graph convolutional network (HLA-GCN) is introduced to find the candidate areas for strap removal, and one area is selected based on scoring. This process is applied twice to reduce the candidates for strap removal, and one strap is finally chosen after identifying the actual impact on IR-drop and routing congestion. This method is enabled by fast incremental IR-drop analysis using PDN-GCN, which classifies nodes with voltage change to update only those nodes in the modified nodal analysis. Experimental results address that the proposed method reduces routing overflow by 16% in an acceptable time, where IR-drop values are updated quickly with high accuracy of less than 2% error.

Interconnect stack parameters are commonly determined before circuit design. But the parameter optimization for a given circuit can improve circuit characteristics, as the parameters greatly affect wire resistance and capacitance. In this paper, we propose a method to select the optimal set of interconnect stack parameters using genetic algorithm. Genetic algorithm takes a long time to generate samples through multiple iterations. We accelerate the convergence to the best solution by reducing the number of parameters and sampling the initial population with the consideration of parameter impact. The experimental results demonstrate that the proposed method shows 1.5% increase in clock frequency and 1.7% reduction in power consumption on average of test circuits, which is 0.3% and 0.6% further improved results compared to naive genetic algorithm. This translates to 80% runtime reduction on the same improvement.

Airgap formed in intermetal dielectric (IMD) reduces coupling capacitance, and thus can be utilized for timing optimization. Metal layers with airgap are limited due to high cost of airgap formation. Layer reassignment is to relocate some timing critical wires in nonairgap layers to airgap layers while noncritical wires in airgap layers are reassigned to nonairgap layers. Airgap insertion is to determine the amount of airgaps that are inserted for each critical wires in airgap layers. The two problems are solved in unified fashion with a goal of maximizing setup total negative slack (TNS) while satisfying hold constraints and design rules. They can be formulated as mixed-integer quadratically constrained programming (MIQCP). So, for practical application, a heuristic algorithm is presented and is experimentally compared to MIQCP with small examples. The experiments demonstrate that setup TNS and setup worst negative slack (WNS) are improved by 37% and 8%, respectively; they are improved by 26% and 5% with a simple-minded approach. The algorithm is also parallelized for application to larger circuits; runtime is decreased by 69% with eight threads.

Circuits that are placed with very low (or high) aspect ratio are susceptible to routing overflows. Such designs are difficult to close and usually end up with larger area with low area utilization. In this article, we propose two routability optimization methods to implement designs even with very low (or high) aspect ratio and high area utilization. First, we find the best assignment of non-uniform placement utilization through convolutional neural network model, and cell placement is performed while respecting the placement utilization. This allows many cells to be spread out over the entire design rather than being centered. The experiments show that most overflows of 16.5% occurring in cell placement are removed with 23.1% reduction in wire length; this is the result of further improving overflow of 9.8% compared to a conventional method. In the second, some flip-flops are selectively stacked to reduce the routing resources used for clock routing. U-Net model is built with graph attention network to predict the congestion after clock-tree synthesis, and the flip-flops in highly congested areas are selected for stacking. The proposed method improves the overflows, which occurs after clock-tree synthesis, by 22.1%.

Circuits that are placed with very low (or high) aspect ratio are susceptible to routing overflows. Such designs are difficult to close and usually end up with larger area with low area utilization. We observe that non-uniform setting of utilization target greatly helps in these designs, specifically low utilization in the center and gradually higher utilization toward the ends. We introduce a convolutional neural network (CNN) model to predict the setting of utilization target values. Experiments indicate that routing congestion overflows are reduced by 29% on average of test designs with 40% reduction in wirelength.

Dynamic IR drop analaysis is very time consuming, so it is only applied in signoff stage before tapeout. U-net model, which is an image-to-image translation neural network, is employed for quick analysis of dynamic IR drop. A number of feature maps are used for u-net input: a map of effective PDN resistance seen from each gate, a map of current consumption of each gate (in particular time instance), and a map of relative distance to nearest power supply pad. A layout is partitioned into a grid of regions and IR drop is predicted region-by-region. For fast prediction, (1) analysis is performed only in time windows which are estimated to cause high IR drop, and (2) effective PDN resistance is approximated through a proposed simplification method. Experiments with a few test circuits demonstrate that dynamic IR drop is predicted 20 times faster than commercial analysis package with 15% error.

Airgap is an intentional void formed in inter-metal dielectric (IMD). It brings about reduced coupling capacitance, and so can be used to improve circuit timing. Airgap can be utilized in a limited number of metal layers due to its high process cost. For given airgap layers, two problems should be addressed to insert airgap: relocate some metal segments in non-airgap layers into airgap layers (called layer reassignment) and determine the amount of airgap for each metal segment in airgap layers (airgap insertion). Two problems are solved together in this paper with a goal of maximizing setup total negative slack (TNS) while assuring no hold violations. It is formulated as mixed integer quadratically constrained programming (MIQCP); heuristic algorithm is proposed for practical application and its performance against MIQCP is experimentally assessed using small test circuits. Experiments demonstrate that TNS and WNS are improved by 35% and 10%, respectively, while simple minded approach achieves 6% and 4% less improvements compared to the proposed method.

Placement-aware synthesis, which combines logic synthesis with virtual placement and routing (P&R) to better take account of wiring, has been popular for timing closure. The wirelength after virtual placement is correlated to actual wirelength, but correlation is not strong enough for some chosen paths. An algorithm to predict the actual wirelength from placement-aware synthesis is presented. It extracts a number of parameters from a given virtual path. A handful of synthetic parameters are compiled through linear discriminant analysis (LDA), and they are submitted to a few machine learning models. The final prediction of actual wirelength is given by the weighted sum of prediction from such machine learning models, in which weight is determined by the population of neighbors in parameter space. Experiments indicate that the predicted wirelength is 93% accurate compared to actual wirelength; this can be compared to conventional virtual placement, in which wirelength is predicted with only 79% accuracy.

Airgap technology enables air to be introduced in inter-metal dielectric (IMD). Airgap between certain wires reduces coupling capacitance due to the reduced permittivity; this can be utilized to decrease circuit delay. We propose an integrated approach of airgap insertion with the goal of circuit timing optimization. It consists of three sub-problems. We first select the layers that employ airgap, called airgap layers, that maximize total negative slack (TNS) improvement; this yields TNS improvement of 7% to 15% and worst negative slack (WNS) improvement of 2% to 8%, compared to a simple assumption of airgap layers. Second, we reassign the layers of wires such that more wires on critical paths can be placed in airgap layers. This is formulated as integer linear programming (ILP), and a more practical heuristic algorithm is also proposed. It provides an additional 17% TNS improvement and 6% WNS improvement. Finally, we perform airgap insertion through ILP formulation, where a number of design rules are modeled with linear constraints. To reduce the heavy runtime of ILP, a layout partitioning technique is also applied. It implements a feasible airgap mask in a manageable time where the amount of inserted airgap is close to the optimal solution.

Redundant via (RV) insertion helps prevent via defects and hence leads to yield enhancement. However, RV insertion in self-aligned double patterning (SADP) processes is challenging since cut optimization has to be considered together. In SADP, parallel one-dimensional metal lines are divided into signal wires and dummy wires by line-end cuts. If an RV is inserted, signal wires need to be extended to connect to the RV. To this end, an additional cut, which we call RV cut, is introduced to make a space for the extension. Since RV cuts and line-end cuts are manufactured with the same mask set, design rules between those cuts have to be honored, which incurs proper distribution and mask assignment to individual cuts. In this article, we address a problem of integrated RV insertion and cut optimization. We show that the problem can be formulated as an integer linear programming (ILP). We also propose a heuristic algorithm is presented for practical application, in which potential locations of RVs are first identified and used to properly insert as many RVs as possible while minimizing the conflict between RV cuts. Our experimental results demonstrate that 75% of vias receive RVs with 8% increase in total wire length, which is only slightly worse than the optimal result obtained by ILP.

Airgap is a technology that enables air to be used as IMD (inter metal dielectric). It brings about reduced coupling capacitance, which helps reduce circuit delay and power consumption. Airgap is constrained by a number of design rules. Manual insertion of airgap while design rules are all respected is inconvenient and time consuming. We address automatic airgap insertion in this paper, in which the goal is to insert maximum amount of airgap in selected paths (e.g. timing critical paths) while related design rules are all honored. Our approach consists of three steps: (1) layout is decomposed into a set of sublayouts, such that airgap can be inserted in each sublayout independently, (2) each of large sublayouts is further partitioned in heuristic fashion, and (3) airgap insertion in each sublayout (or each partition of sublayout) is performed through ILP (integer linear programming). Experiments indicate that runtime is manageable; the impact of airgap on circuit delay is also demonstrated, e.g. 5.6% improvement of worst slack on average of test circuits.

A non-tree clock network, such as crosslink and mesh, includes some shorted wires to reduce clock skew. A short-circuit current that flows through the shorted wires makes conventional static timing analysis (STA) inapplicable. Transistor-level simulation may be applied but takes long time. We address a fast timing analysis of non-tree clock network. A partial circuit made of drivers, shorted wires, and receivers is extracted and represented as voltagedependent current sources with π-model of RC load. Given voltage waveforms at driver inputs, we calculate the waveform at each shorted node by repeating nodal analysis for each time step; the waveform is represented as piecewise linear function. As the waveform propagates to receiver input via RC tree, the responses for all linear segments are obtained and merged into a full waveform. The waveform at receiver input then passes through receiver to produce a linear waveform at receiver output. Finally, timing parameters from the waveform at receiver output are transferred to STA, such that it utilizes the parameters to analyze the remaining circuit from receiver outputs to clock sinks. Experiments with a few test circuits demonstrate that analysis time is reduced by 10× with only 1% error on average (both in delay and transition time) compared to SPICE.

A circuit operating at near-threshold voltage (NTV) dissipates much less energy, but it suffers from significant increase in cell delay as well as delay variation. In this paper, we address two library optimization methods for NTV design: (1) transistor lengths are increased to benefit from reverse short channel effect (RSCE), and (2) each flip-flop is optimized into a few versions with different timing parameters by redistributing clock signals to clocked transistors. Flip-flops are remapped to optimized ones via integer linear programming (ILP); a goal is to minimize total negative slack (TNS) under hold time constraints, which is a critical concern in NTV design. Experiments demonstrate that our proposed method achieves 22%, 56%, and 13% reductions in clock period, energy dissipation, and circuit area, respectively, on average of a few test circuits in 55-nm technology.

Buffer insertion to remove hold violations at multiple process corners is addressed for the first time. The problem is formulated as integer linear programming (ILP); it is combined with circuit partitioning heuristic so that larger circuits can also be handled. A heuristic buffer insertion algorithm is then proposed and compared to ILP, which demonstrates only a slight increase of the number of buffers (2.4% on average). Two additional intuitive methods are implemented to demonstrate why new heuristic algorithm is needed: conventional buffer insertion at each process corner one by one and conventional buffer insertion at all process corners simultaneously followed by combining insertion results.

With the current DNA nanotechnology, we are now able to arrange DNA molecules on a DNA origami to compose a logic gate. This in turn realizes a spatially localized DNA circuit, on which the logic gates are placed on the specific locations as in electronic circuits. In this paper, we address three key problems in designing large-scale spatially localized DNA circuits. An AND gate, made of four hairpins, functions in stochastic manner and sometimes outputs a wrong result. Given tolerable error probability at each circuit output, we address how the probability that each AND gate functions correctly can be determined, which in turn determines the location of constituent hairpins. In the second problem, we study how hairpins are arranged on a DNA origami to minimize the area of a whole circuit, which determines the area of the origami board. The third problem regards the DNA domain assignment so that connected gates can communicate without interference.