The increasing application of robots in the workplace has made employee collaboration with robots a prevalent phenomenon. Existing literature on human-robot collaboration has both implicitly and explicitly highlighted the benefits of such collaboration, such as promoting efficiency and productivity. Drawing upon self-regulation theory, this study challenges this prevailing assumption by revealing a potential dark side of employee collaboration with robots, specifically its potential to lead to burnout. Our findings, derived from an experiment and a multi-wave field survey, demonstrate that employee collaboration with robots can lead to a self-esteem threat, which in turn results in burnout. Moreover, the perceived intelligence of robots moderated the indirect effect of employee collaboration with robots on burnout through self-esteem threat. This effect was more pronounced when the perceived intelligence of robots was high, as opposed to low. This study offers fresh insights into the consequences of employees collaborating with robots. It also highlights the need for future research to focus on the psychological well-being of employees engaged in such collaborations.

As robots are increasingly capable of performing tasks typically performed by humans and are becoming more human-like, the comparison of humans with robots by organizational leaders is, therefore, becoming increasingly prevalent in the workplace. However, existing literature offers very limited insight into the potential effects of such behaviors in a human–robot collaboration setting. In this research, we explore how and for whom leaders’ human–robot comparison behavior affects subordinate counterproductive work behavior (CWB). Drawing upon dehumanization theory, we propose that leaders’ human–robot comparison behavior increases subordinate perceived dehumanization, which in turn promotes their subsequent CWB. We further propose that subordinates’ need for uniqueness amplifies the positive indirect effect of leaders’ human–robot comparison behavior on subordinate CWB through perceived dehumanization. Results from an experiment (Study 1) and a multi-source, multi-wave field study (Study 2) converged to support our predictions. We discuss the theoretical and practical implications of these findings and propose future research directions.

Recently, graph neural network (GNN) has shown significant strength in predicting the quantum mechanical properties of molecules. Based on GNN, the DimeNet++ leverages both distance information of atomic pairs and angle information of atomic triplets via message passing mechanism to predict quantum mechanical properties of molecules and has achieved state-of-the-art results. However, there are more than 10 thousand operators in DimeNet++, which results in low GPU utilization and large CPU launch overhead. The extensive time taken for the training of DimeNet++ is a significant drawback. The training period of DimeNet++ exceeds one month on a single NVIDIA A100 GPU. A common method for reducing training time involves employing data parallelism, which equally distributes the global batch across each GPU. However, data-parallel task partitioning, by default, does not consider load imbalance within the batch. This load imbalance leads to considerable synchronization overhead in a multi-GPU setting, reducing the overall efficiency of the parallelism. For the strong-scaling scenario, it results in 32% of the compute resource being wasted. In light of these observations, we propose a novel approach, FastDimeNet++, which delivers high GPU utilization, low CPU overhead, and extensive scalability, achieved through a series of optimization strategies. These include (i) a communication-free load-balancing sampler, (ii) computation graph reconstruction, and (iii) kernel fusion and redundancy bypass. Our experiments demonstrate that FastDimeNet++ achieves a GPU utilization rate of approximately 88% based on a mini-batch size of 4. Furthermore, we scale FastDimeNet++ to 512 GPUs, reaching 2.8 PetaFLOPS. In the MLPerf HPC V1.0, the winning DimeNet++ submission required a total training time of 111.86 minutes, whereas FastDimeNet++ introduced for the MLPerf HPC V2.0 required just 21.93 minutes, demonstrating a significant performance improvement of over 5 ×.

Fast and accurate design-space exploration is a critical requirement for enabling future hardware designs. However, big-data applications are often complex targets to evaluate on early performance models (e.g., simulators or RTL models) owing to their complex software-stacks, significantly long run times, system dependencies and the limited speed of performance models. To overcome the challenges in benchmarking complex big-data applications, in this paper, we propose a proxy generation methodology, CAMP that can generate miniature proxy benchmarks, which are representative of the performance of bigdata applications and yet converge to results quickly without needing any complex software stack support. Prior system-level proxy generation techniques model core locality features in detail, but abstract out memory locality modeling using simple stridebased models, which results in poor cloning accuracy for most applications. CAMP accurately models both core-performance and memory locality, along with modeling the feedback loop between the two. CAMP replicates core performance by modeling the dependencies between instructions, instruction types, control-flow behavior, etc. CAMP also adds a memory locality profiling approach that captures spatial and temporal locality of applications. Finally, we propose a novel proxy replay methodology that integrates the core and memory locality models to create accurate system-level proxy benchmarks. We demonstrate that CAMP proxies can mimic the original application's performance behavior and that they can capture the performance feedback loop well. For a variety of real-world big-data applications, we show that CAMP achieves an average cloning accuracy of 89%. We believe this is a new capability that can facilitate for overall system (core and memory subsystem) design exploration.

Recent research studies have shown that modern GPU performance is often limited by the memory system performance. Optimizing memory hierarchy performance requires GPU designers to draw design insights based on the cache & memory behavior of end-user applications. Unfortunately, it is often difficult to get access to end-user workloads due to the confidential or proprietary nature of the software/data. Furthermore, the efficiency of early design space exploration of cache & memory systems is often limited due to either the slow speed of detailed simulation techniques or limited scope of state-of-the-art cache analytical models.

Fast and accurate performance estimation is a key challenge in modern system design. Recently, machine learning-based approaches have emerged that allow predicting the performance of an application on a target platform from executions on a different host. However, existing approaches rely on expensive instrumentation that requires source code to be available. We propose a novel sampling-based, binary-level cross-platform prediction method that accurately predicts performance of a workload on a target by relying on various performance statistics sampled on a host using built-in hardware counters. In our proposed framework, samples acquired from the host and target do not satisfy straightforward one-to-one correspondence that characterizes prior instrumentation-based approaches. The resulting alignment problem is NP-hard; to solve it efficiently, we develop a stochastic dynamic coupling (SDC) algorithm which, under mild assumptions, with high probability closely approximates optimal alignment. The prediction model constructed using SDC-aligned samples achieves on average 96.5% accuracy for 45 benchmarks at speeds of over 3 GIPS. At similar accuracies, this is up to 6× faster than instrumentation-based prediction, and approximately twice the speed of executing the same applications natively on our ARM target.

With increasing memory footprints and working set sizes of emerging workloads, system designers need to evaluate new memory hierarchies with large last level caches (LLCs), DRAM caches, large DRAMs, etc. to optimize performance gains. This requires a deep understanding of the memory access behavior of the target workloads. It is important to have accurate mechanisms to generate address streams to study memory access behavior at and beyond LLCs. Prior memory trace generation proposals such as WEST and STM utilize LRU stack distance to capture temporal locality in the data access streams. In addition, STM also captures spatial locality information by modeling stride-based access patterns. However, a key drawback of prior models is that the metadata that they store to capture locality is significantly high. In this paper, we propose an efficient, light-weight methodology to generate accurate traces for modeling address Streams for LLC And Beyond (SLAB). SLAB leverages the key insight that memory access patterns can be efficiently characterized by combining locality and reuse statistics captured from both instruction and address streams. Compared to prior studies, which capture patterns solely based on data addresses, using the additional instruction stream localized information significantly reduces the space complexity. For programs where dominant instruction-localized patterns do not exist, SLAB exploits multi-granularity data reuse distances. We evaluate SLAB using SPEC CPU2006 and Cloudsuite benchmarks. With meta-data sizes of less than 7% of the original LLC traces, SLAB demonstrates over 91% accuracy in replicating original application behavior across ~9000 different cache, prefetcher and memory configurations.

In modern cloud computing and analytics applications, large-scale data is often represented in the form of graphs. Many recent works have focused on understanding and improving performance of graph processing frameworks. Power consumption, which also serves as a key factor in the deployment and management of graph processing frameworks, has not been extensively studied. In this paper, we demonstrate the use of an online software power estimation tool that is capable of obtaining fine-grained power traces. By leveraging component-level power behavior, we show that static power consumption still constitutes a significant portion of the total power. Moreover, we illustrate the impact of various dynamic voltage and frequency scaling polices on these workloads, and observe that setting the computing node to its maximum frequency can achieve optimal performance and energy consumption. From our analysis on the impact of machine scale-up, we conclude that computing nodes with small number of computing threads consume more energy than the powerful ones. This observation can help cloud administrators on energy-efficient resource allocation.

Fast and accurate performance and power prediction is a key challenge in co-development of hardware and software. Traditional analytical or simulation-based approaches are often too inaccurate or slow. In this work, we propose LACross, a novel learning-based, analytical cross-platform prediction framework that provides fast and accurate estimation of time-varying software performance and power consumption on a target hardware platform. We employ a fine-grained phase-based approach, where the learning algorithm synthesizes analytical proxy models that predict the performance and power of the workload in each program phase from performance statistics obtained through hardware counter measurements on the host. Our learning approach relies on a one-time training phase using a target reference model or real hardware. We applied our approach to 35 benchmarks from SPEC 2006, SD-VBS and MiBench. Results show on average over 97% prediction accuracy for predicting both fine-grain performance and power traces at speeds of over 500 MIPS.

Big data decision-making techniques take advantage of large-scale data to extract important insights from them. One of the most important classes of such techniques falls in the domain of graph applications, where data segments and their inherent relationships are represented as vertices and edges. Efficiently processing large-scale graphs involves many subtle tradeoffs and is still regarded as an open-ended problem. Furthermore, as modern data centers move towards increased heterogeneity, the traditional assumption of homogeneous environments in current graph processing frameworks is no longer valid. Prior work estimates the graph processing power of heterogeneous machines by simply reading hardware configurations, which leads to suboptimal load balancing. In this paper, we propose a profiling methodology leveraging synthetic graphs for capturing a node's computational capability and guiding graph partitioning in heterogeneous environments with minimal overheads. We show that by sampling the execution of applications on synthetic graphs following a power-law distribution, the computing capabilities of heterogeneous clusters can be captured accurately (<;10% error). Our proxy-guided graph processing system results in a maximum speedup of 1.84x and 1.45x over a default system and prior work, respectively. On average, it achieves 17.9% performance improvement and 14.6% energy reduction as compared to prior heterogeneity-aware work.