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Lena E. Olson

dblp:173/9798 · DBLP profile ↗
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3ranked-venue papers
2as first author
0since 2021 · last 2019
0000-0002-5089-5688ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-authorSoftware engineering, systems software and programming languages · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Cloud and datacenter computing · 53% Hardware accelerators and domain-specific architectures · 24% Memory systems · 24%
Network and information security
1 paper
Hardware security and side channels · 77% Systems and software security · 23%
Software engineering, system software, and programming languages
1 paper
Operating systems · 100%

Topics — the 8 heaviest of 10, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Cloud and datacenter computing
datacenter network
0.412019
Snap: a microkernel approach to host networking · SOSP 2019
Cloud and datacenter computing › virtualization › network virtualization
network function virtualization
0.412019
Snap: a microkernel approach to host networking · SOSP 2019
Cloud and datacenter computing
userspace networking
0.412019
Snap: a microkernel approach to host networking · SOSP 2019
Memory systems
cache coherence
0.312017
Crossing Guard: Mediating Host-Accelerator Coherence Interactions · ASPLOS 2017
Hardware accelerators and domain-specific architectures
accelerator integration
0.212015
Border control: sandboxing accelerators · MICRO 2015
Memory systems › virtual memory management
shared virtual memory
0.212015
Border control: sandboxing accelerators · MICRO 2015
Operating systems › kernel › kernel design › microkernel
microkernel design
0.112019
Snap: a microkernel approach to host networking · SOSP 2019
Systems and software security
memory protection
0.112015
Border control: sandboxing accelerators · MICRO 2015

Methods — techniques the papers use, named apart from their topics

kernel bypass · 0.8RDMA · 0.8
YearPublicationVenuePosition
2019 Snap: a microkernel approach to host networking
abstract
This paper presents our design and experience with a microkernel-inspired approach to host networking called Snap. Snap is a userspace networking system that supports Google's rapidly evolving needs with flexible modules that implement a range of network functions, including edge packet switching, virtualization for our cloud platform, traffic shaping policy enforcement, and a high-performance reliable messaging and RDMA-like service. Snap has been running in production for over three years, supporting the extensible communication needs of several large and critical systems.
Michael Marty, Marc de Kruijf, Jacob Adriaens, Christopher Alfeld, Sean Bauer, Carlo Contavalli, Michael Dalton, Nandita Dukkipati, William C. Evans, Steve D. Gribble, Nicholas Kidd, Roman Kononov, Gautam Kumar 0001, Carl Mauer, Emily Musick, Lena E. Olson, Erik Rubow, Michael Ryan, Kevin Springborn, Valas Valancius, Amin Vahdat
SOSP16
2017 Crossing Guard: Mediating Host-Accelerator Coherence Interactions
abstract
Specialized hardware accelerators have performance and energy-efficiency advantages over general-purpose processors. To fully realize these benefits and aid programmability, accelerators may share a physical and virtual address space and full cache coherence with the host system. However, allowing accelerators -- particularly those designed by third parties -- to directly communicate with host coherence protocols poses several problems. Host coherence protocols are complex, vary between companies, and may be proprietary, increasing burden on accelerator designers. Bugs in the accelerator implementation may cause crashes and other serious consequences to the host system.
Lena E. Olson, Mark D. Hill, David A. Wood 0001
ASPLOS1
2015 Border control: sandboxing accelerators
abstract
As hardware accelerators proliferate, there is a desire to logically integrate them more tightly with CPUs through interfaces such as shared virtual memory. Although this integration has programmability and performance benefits, it may also have serious security and fault isolation implications, especially when accelerators are designed by third parties. Unchecked, accelerators could make incorrect memory accesses, causing information leaks, data corruption, or crashes not only for processes running on the accelerator, but for the rest of the system as well. Unfortunately, current security solutions are insufficient for providing memory protection from tightly integrated untrusted accelerators.
Lena E. Olson, Jason Lowe-Power, Mark D. Hill, David A. Wood 0001
MICRO1