Demo Data from EDBT 2026 / reviewers in the wild / expert
Thomas Mullins
dblp:173/9809
· DBLP profile ↗
2ranked-venue papers
0as first author
0since 2021 · last 2017
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Memory systems · 64% Hardware accelerators and domain-specific architectures · 36% |
Topics — the 6 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware accelerators and domain-specific architectures › machine learning accelerator
in-memory computing accelerator |
0.3 | 1 | 2017 | Ambit: in-memory accelerator for bulk bitwise operations using commodity DRAM technology · MICRO 2017 |
Memory systems
processing-in-memory |
0.3 | 1 | 2017 | Ambit: in-memory accelerator for bulk bitwise operations using commodity DRAM technology · MICRO 2017 |
Memory systems
DRAM |
0.2 | 1 | 2015 | Gather-scatter DRAM: in-DRAM address translation to improve the spatial locality of non-unit strided accesses · MICRO 2015 |
Memory systems
memory access patterns |
0.2 | 1 | 2015 | Gather-scatter DRAM: in-DRAM address translation to improve the spatial locality of non-unit strided accesses · MICRO 2015 |
Memory systems › memory access patterns
strided access |
0.2 | 1 | 2015 | Gather-scatter DRAM: in-DRAM address translation to improve the spatial locality of non-unit strided accesses · MICRO 2015 |
Memory systems › data locality
spatial locality |
0.1 | 1 | 2015 | Gather-scatter DRAM: in-DRAM address translation to improve the spatial locality of non-unit strided accesses · MICRO 2015 |
Methods — techniques the papers use, named apart from their topics
bulk-bitwise operation · 0.3DRAM technology · 0.3address translation · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2017 | Ambit: in-memory accelerator for bulk bitwise operations using commodity DRAM technologyabstractMany important applications trigger bulk bitwise operations, i.e., bitwise operations on large bit vectors. In fact, recent works design techniques that exploit fast bulk bitwise operations to accelerate databases (bitmap indices, BitWeaving) and web search (BitFunnel). Unfortunately, in existing architectures, the throughput of bulk bitwise operations is limited by the memory bandwidth available to the processing unit (e.g., CPU, GPU, FPGA, processing-in-memory). Vivek Seshadri, Donghyuk Lee, Thomas Mullins, Hasan Hassan, Amirali Boroumand, Jeremie S. Kim, Michael A. Kozuch, Onur Mutlu, Phillip B. Gibbons, Todd C. Mowry |
MICRO | 3 |
| 2015 | Gather-scatter DRAM: in-DRAM address translation to improve the spatial locality of non-unit strided accessesabstractMany data structures (e.g., matrices) are typically accessed with multiple access patterns. Depending on the layout of the data structure in physical address space, some access patterns result in non-unit strides. In existing systems, which are optimized to store and access cache lines, non-unit strided accesses exhibit low spatial locality. Therefore, they incur high latency, and waste memory bandwidth and cache space. Vivek Seshadri, Thomas Mullins, Amirali Boroumand, Onur Mutlu, Phillip B. Gibbons, Michael A. Kozuch, Todd C. Mowry |
MICRO | 2 |