Yuyang Zhu

dblp:174/0570 · DBLP profile ↗
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6ranked-venue papers
2as first author
4since 2021 · last 2025
—ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 2 first-author · 3 since 2021Artificial intelligence and machine learning · 2Graphics, computer vision, multimedia, augmented reality and games · 1 · 1 since 2021
YearPublicationVenuePosition
2025 Design of a 1-5GHz Inverter-Based Phase Interpolator for Spin-Wave Detection
abstract
This paper details the design and implementation of a wide-band, digital-controlledinverter-based phase interpolator (PI) for a spin-wave detection circuit. The PI contains input phase generation part for coarse phase tunning, and PI core part for fine phase tunning. Fabricated using 65nm CMOS technology, the circuit operates across a frequency range of 1GHz to 5GHz with a 1V supply. The chip is implemented in 65nm CMOS technology and operates from 1GHz to 5GHz, with 1V supply. The power consumption of the proposed PI core is 1.89mW at 5GHz. The measured differential non-linearity and integral non-linearity are 0.6 LSB and 5.17 LSB respectively at the worst case.
Yuyang Zhu, Zunsong Yang, Zhenyu Cheng 0003, Md Shamim Sarker, Hiroyasu Yamahara, Munetoshi Seki, Hitoshi Tabata, Tetsuya Iizuka
ASP-DAC1
2025 Optimization of DTC-Based and Harmonic-Mixer-Based Fractional-N PLLs: Comparative Analysis of Jitter and Power Trade-Offs
abstract
As phase-locked loop (PLL) architectures become increasingly complex, optimizing the jitter and power performance through calculation alone is becoming more challenging for fractional-N PLLs. To find the most suitable PLL architecture that meets the jitter-power requirements of various applications, a simple and widely-applicable method is in demand to find the optimal jitter-power relation of different PLL architectures. In this paper, we propose the use of a multi-objective evolutionary algorithm (MOEA) to optimize the jitter and power of PLLs, specifically focusing on two popular fractional-N PLL architectures: digital-to-time converter (DTC)-based and harmonic-mixer (HM)-based PLLs. By applying the MOEA, we can achieve optimal jitter and power relationships for both architectures, and the observed trends in jitter and power are explained and supported with calculations.
Yuyang Zhu, Masaru Osada, Tetsuya Iizuka
IEEE Trans. Circuits Syst. I Regul. Pap.1
2025 A Sparse Function Prediction Approach for Cold Start Optimization and User Satisfaction Guarantee in Serverless
abstract
Serverless computing relies on keeping functions alive or pre-warming them before invocation to mitigate the cold start problem, stemming from the overhead of initializing function startup environments. However, under constrained cloud resources, accurately predicting the invocation patterns of sparse functions remains challenging. This limits the formulation of effective pre-warm and keep-alive strategies, leading to frequent cold starts and degraded user satisfaction. To address these challenges, we proposeSPFaaS, a hybrid framework based on sparse function prediction. To enhance the learnability of sparse function invocation data,SPFaaStakes into account the characteristics of cloud service workloads along with the features of pre-warm and keep-alive strategies, transforming function invocation records into probabilistic data. It captures the underlying periodicity and temporal dependencies in the data through multiple rounds of sampling and the combined use of Gated Recurrent Units and Temporal Convolutional Networks for accurate prediction. Based on the final prediction outcome and real-time system states,SPFaaSdetermines adaptive pre-warm and keep-alive strategies for each function. Experiments conducted on two real-world serverless clusters demonstrate thatSPFaaSoutperforms state-of-the-art methods in reducing cold starts and improving user satisfaction.
Wang Zhang 0002, Yuyang Zhu, Zhan Shi 0001, Manyu Dang, Yutong Wu 0013, Fang Wang 0001, Dan Feng 0001
IEEE Trans. Parallel Distributed Syst.2
2022 Dynamic Sliding Window for Realtime Denoising Networks
abstract
Realtime speech denoising has been long studied. Almost all existing methods process the incoming data stream using a sliding window of fixed-size. Yet, we show that the use of fixed-size sliding window may lead to an accumulating lag, especially in presence of other background computing processes that may occupy CPU resources. In response, we propose a new sliding window strategy and a lightweight neural network to leverage it. Our experiments show that the proposed approach achieves denoising quality on a par with the stateof-the-art realtime denoising models. More importantly, our approach is faster, maintaining a stable realtime performance even when the available computing power fluctuates.
Jinxu Xiang, Yuyang Zhu, Rundi Wu, Ruilin Xu 0001, Yuko Ishiwaka, Changxi Zheng
ICASSP2
2020 Discriminative Analysis of Symptom Severity and Ultra-High Risk of Schizophrenia Using Intrinsic Functional Connectivity
abstract
Past studies have consistently shown functional dysconnectivity of large-scale brain networks in schizophrenia. In this study, we aimed to further assess whether multivariate pattern analysis (MVPA) could yield a sensitive predictor of patient symptoms, as well as identify ultra-high risk (UHR) stage of schizophrenia from intrinsic functional connectivity of whole-brain networks. We first combined rank-based feature selection and support vector machine methods to distinguish between 43 schizophrenia patients and 52 healthy controls. The constructed classifier was then applied to examine functional connectivity profiles of 18 UHR individuals. The classifier indicated reliable relationship between MVPA measures and symptom severity, with higher classification accuracy in more severely affected schizophrenia patients. The UHR subjects had classification scores falling between those of healthy controls and patients, suggesting an intermediate level of functional brain abnormalities. Moreover, UHR individuals with schizophrenia-like connectivity profiles at baseline presented higher rate of conversion to full-blown illness in the follow-up visits. Spatial maps of discriminative brain regions implicated increases of functional connectivity in the default mode network, whereas decreases of functional connectivity in the cerebellum, thalamus and visual areas in schizophrenia. The findings may have potential utility in the early diagnosis and intervention of schizophrenia.
Yuyang Zhu, Bei Lin, Qijing Bo, Chuanyue Wang
Int. J. Neural Syst.3
2016 A recurrent neural network for modeling crack growth of aluminium alloy
Linxian Zhi, Yuyang Zhu, Hai Wang 0004, Zhengming Xu, Zhihong Man
Neural Comput. Appl.2