In this paper, a novel Asymptotic Probability Approximation (APA) method is proposed to estimate the overall rare probability of correlated failure events for complex circuits containing a large number of replicated cells (e.g., SRAM bit-cells). The key idea of APA is to approximate the overall circuit failure rate based on a set of carefully defined failure events. An efficient Hierarchal Subset Simulation (H-SUS) method is developed to calculate the aforementioned failure rate and a statistical methodology is further proposed to estimate the confidence interval of APA. Our numerical experiments demonstrate that APA can accurately and reliably estimates the overall failure rate of correlated rare failure events involving more than 20,000 independent random variables.

Efficient performance modeling is an extremely important task for yield analysis and design optimization of analog circuits. In this paper, a novel regression modeling method based on hierarchical shrinkage priors is proposed to construct hybrid performance models with both high accuracy and low computational cost. In particular, the user-defined model templates derived from design equations and the general-purpose orthogonal polynomials are combined together to set up a hybrid dictionary. Next, in order to avoid over-shrinking large model coefficients, a novel regression method based on hierarchical shrinkage priors and variational Bayesian inference is adopted for model fitting. A rail-to-rail operational amplifier example demonstrates that the proposed method achieves up to 40% error reduction over other state-of-the-art approaches without increasing the modeling cost.

In this paper, we propose a novel spatial variation modeling method based on hidden Markov tree (HMT) for nanoscale integrated circuits, which could efficiently improve the accuracy of full-wafer/chip spatial variations recovery at extremely low measurement cost. Applying this method, HMT is introduced to set up a statistical model for coefficients after exploring the underlying correlated representation of the spatial variation in the frequency domain. Accordingly, two key inherent properties of the modeling coefficients, i.e., correlations and sparse presentations in the frequency domain, can be captured exactly and the modeling accuracy can be improved evidently. Then, maximum-a-posteriori estimation is applied to formulate the original problem as a convex optimization that could be solved efficiently and robustly. Numerical results based on industrial data demonstrate that the proposed method can achieve superior accuracy over other existing approaches including orthogonal matching pursuit, l1-norm regularization, and reweighted l1-norm regularization.

Efficiently optimizing large-scale, complex analog systems requires to know the performance tradeoffs for various analog circuit blocks. In this paper, we propose a radically new approach for analog performance tradeoff modeling. Our key idea is to broadly search the rich design knowledge from the Internet, and then mathematically encode the knowledge as high-dimensional performance tradeoff curves that are referred to as Pareto fronts in the literature. Toward this goal, several novel numerical algorithms, such as sparse regression and semi-infinite programming, are developed in order to construct the high-dimensional Pareto front model while guaranteeing its monotonicity. Our numerical examples demonstrate that the proposed modeling technique can accurately capture the high-dimensional Pareto fronts for large-scale analog systems (e.g., analog-to-digital converter) while most traditional methods are limited to low-dimensional Pareto front modeling of small circuit blocks without considering layout parasitics and manufacturing nonidealities.