Fault tolerance is vital in many domains. One popular way to increase fault-tolerance is through hardware redundancy. However, basic redundancy cannot cope with Common Mode Failures (CMFs). One way to address CMF is through the use of diversity in combination with traditional hardware redundancy. This work proposes an automatic design space exploration (DSE) method to generate optimized redundant hardware accelerators with maximum diversity to protect against CMFs given as a single behavioral description for High-Level Synthesis (HLS). For this purpose, this work exploits one of the main advantages of C-based VLSI design over the traditional RT-level design based on low-level Hardware Description Languages (HDLs): The ability to generate micro-architectures with unique characteristics from the same behavioral description. Experimental results show that the proposed method provides a significant diversity increment compared to using traditional RTL-based exploration to generate diverse designs.

This paper presents an FPGA-based hardware acceleration of the design diversity calculation to build robust redundant hardware systems against common model failures. We exploit the benefits of C-based VLSI design to generate a design pool of micro-architectures with unique characteristics from the same behavioral description. To identify the most diverse design pairs from this massive design pool, a computationally-intensive fault-injection based process is needed. Thus, in this work, we leverage the use of FPGAs to accelerate the design diversity calculation. Experimental results show an average of 2x speedup compared to a traditional software implementation. We also show that much higher speedups can be achieved when using larger FPGAs that can host a larger pool of designs.

High-Level Synthesis (HLS) allows the automatic generation of hardware accelerators with unique design metrics. This work leverages this unique feature and presents a method to increase the search space of fault-tolerant hardware accelerators. The proposed method is based on a two-stage approach that automatically generates Pareto-optimal configurations for the hardware accelerators with different area, performance and reliability to mitigate the effect of soft errors. The first stage performs a source-to-source transformation on the behavioral description to annotate the N-modular redundancy directly at the source code including the voter, while the second stage then performs a HLS design space exploration (DSE) on this newly obtained behavioral description. Compared to performing the exploration on a single module and then replicating the accelerator N times, the proposed exploration strategy leads to a much richer search space. Experiments show that our proposed method leads to better results compared to the state-of-the-art by expanding the search space considerably.

Hardware redundancy techniques are extensively used for enhancing system reliability, availability and fault tolerance. However, traditional identical module N-modular redundancy (NMR) cannot protect against Common Mode Failures (CMFs). One method that has been proposed to protect against CMFs is the use of dissimilar (diverse) module redundancy. One of the problems with previous work is that it generates these diverse modules by perturbing the gate-netlist and thus, achieve very limited diversity. In addition, previous work is very time consuming as it requires to insert fault-pairs in the gate-netlists in order to measure the effect of these on the outputs. To address these issues, this work proposes to first increase diversity by raising the level of abstraction from the gate level to the behavioral level. Secondly, we propose a fast machine learning based method that facilitates the design space exploration (DSE) of single behavioral descriptions in order to generate optimized redundant hardware accelerator system with maximum diversity to protect against CMFs. For this purpose, this work exploits one of the main advantages of C-based VLSI design: The ability to generate micro-architectures with unique characteristics from the same behavioral description by setting different synthesis directives in the form of pragmas. Experimental results show that our proposed method is a fast and efficient way to generate diverse designs to protect the system against CMFs.

Continuous pursuit of higher performance and energy efficiency has led to heterogeneous SoC that contains multiple dedicated hardware accelerators. These accelerators exploit the inherent parallelism of tasks and are often tolerant to inaccuracies in their outputs, e.g. image and digital signal processing applications. At the same time, permanent faults are escalating due to process scaling and power restrictions, leading to erroneous outputs. To address this issue, in this paper, we propose a low-cost, universal fault-recovery/repair method that utilizes supervised machine learning techniques to ameliorate the effect of permanent fault(s) in hardware accelerators that can tolerate inexact outputs. The proposed compensation model does not require any information about the accelerator and is highly scalable with low area overhead. Experimental results show, the proposed method improves the accuracy by 50% and decreases the overall mean error rate by 90% with an area overhead of 5% compared to execution without fault compensation.

This work proposes an automatic method to generate optimized redundant hardware accelerator with maximum reliability given a single behavioral description for High-Level Synthesis (HLS). For this purpose, this work exploits one of the main advantages of C-based VLSI design over traditional RT- level design: The ability to generate micro-architectures with unique characteristics from the same behavioral description. This is typically done by setting different synthesis options to determine how to synthesize loops, arrays and functions and to specify the number and type of Functional Units (FUs) to be instantiated. The proposed method is composed of two main phases. The first phase performs HLS Design Space Exploration (DSE) leading to a trade-off curve of designs with a unique area, execution time and reliability. The second phase finds the most reliable system given an area and time constraint by either implementing time or space redundancy, or a mixture of both using any combinations of micro-architectures found by the explorer. This second phase has been formulated as an integer linear program (ILP). Experimental results show that the proposed method provides a 20% reliability increase compared to the most common approach of simply using a single micro-architecture and instantiating it multiple times with no significant area or timing overhead.

With process scaling and the adoption of post-CMOS technologies, permanent faults are becoming a fundamental problem. Circuits containing defects are either discarded (reducing yield) or partially disabled (reducing performance). In this paper, we propose a general approach using supervised and discriminative learning techniques to compensate for the effect of permanent faults on a circuit's output. The insight for this approach is that many emerging systems and applications are able to tolerate some loss of quality in their computed results. Therefore, more scalable and lower overhead compensation techniques may be used to approximately correct for the effect of hardware faults on the circuit output. The proposed approach is shown to improve the output quality of complex accelerator and application-specific logic by 2-3 orders of magnitude while incurring