This paper proposes a sample-and-hold amplifier (SHA)-less front-end stage structure suitable for pipeline ADCs in time-interleaving architecture with large interleaving factor. A low resolution SARADC is adopted as the sub-quantizer, and a bridge capacitor is introduced to connect the two capacitor arrays of the MDAC and the sub-ADC. Compared to commonly used pipelined-SAR ADC architectures, the proposed front-end stage structure reduces the reference load on the sub-quantizer during coarse conversion, while preserving the benefits of a shared sampling network in the sampling process. A 14-bit 500-MS/s pipeline ADC channel in an 8-way time-interleaved architecture utilizing the proposed front-end stage structure is designed in 28-nm CMOS process. Simulation results well demonstrate that the proposed front-end stage structure is highly immune to aperture errors, and shows the ADC channel achieves 69.13 dB SNDR and 83.8 dB SFDR at Nyquist frequency. With an estimated power consumption of 40-mW, a Walden FoM of 34.24-fJ/conv.-step is achieved.

This paper presents an improved correlation-based timing-skew calibration strategy with constant input impedance characteristics. A full sampling rate operating time-interleaved reference ADC (TI-RADC) whose interleaving factor is coprime with TI-ADC is introduced to replace the conventional single-channel reference ADC. This paper theoretically demonstrates that by setting an appropriate time interval between the sampling edge of TI-ADC and TI-RADC and aligning the sampling edge of each channel in TI-ADC with each other but not with the reference ADC, the skew of the TI-RADC would not affect the timing skew calibration of the TI-ADC. A prototype 13-bit 2-GS/s 8-way TI pipelined SAR ADC employing a 1-bit 3-way TI-RADC is fabricated in 28-nm process to verify the presented calibration strategy. Measurement results demonstrate the correctness of the calibration strategy and reveal that compared with using single-channel reference ADC operating at a decimated sampling rate, the spurs resulting from the time-variant input impedance are suppressed more than 20 dB. The prototype ADC achieves an SNDR of 60.36 dB with a near Nyquist rate input when operating at 2-GS/s. The power consumption of the prototype ADCis 252.6 mW (Including the 4.1 mW estimated digital calibration), which translates into a Walden FoM of 148.3-fJ/conversion-step.

This article describes a gain-stabilized integration time generation technique suitable for the pipelined successive approximation register (SAR) analog-to-digital converter (ADC) utilizing an open-loop integrator-based residue amplifier (RA). The gain variation of RA under different process, voltage, and temperature (PVT) conditions is alleviated by adaptively adjusting the length of the generated integration time. A 13-bit 312.5-MS/s two-stage pipelined SAR ADC employing the presented technique is fabricated in a 28-nm process. At a sampling rate of 312.5 MS/s, the prototype ADC achieves a 65.1-dB SNDR and a Walden FoM of 13.95 fJ/conversion-step with an over Nyquist input. Less than 1-dB SNDR variation are obtained for supply voltage varying within ±60 mV and the temperature varying from -40 °C to 120 °C, respectively.

A novel energy-efficient data gathering scheme that exploits spatial-temporal correlation is proposed for clustered wireless sensor networks in this paper. In the proposed method, dual prediction is used in the intracluster transmission to reduce the temporal redundancy, and hybrid compressed sensing is employed in the intercluster transmission to reduce the spatial redundancy. Moreover, an error threshold selection scheme is presented for the prediction model by optimizing the relationship between the energy consumption and the recovery accuracy, which makes the proposed method well suitable for different application environments. In addition, the transmission energy consumption is derived to verify the efficiency of the proposed method. Simulation results show that the proposed method has higher energy efficiency compared with the existing schemes, and the sink can recover measurements with reasonable accuracy by using the proposed method.