High-resolution ADCs require low noise and low distortion while consuming minimal power. This paper presents a power-efficient, calibration-free, 2nd-order noise-shaping (NS) SAR ADC. Mismatch error shaping (MES) is employed to reduce distortion from capacitive DAC mismatches. The resulting input range loss is compensated for by an additional digital prediction (DP) method. To mitigate the high power consumption of the multi-input dynamic comparator, this work proposes a coarse-fine comparison (CFC) scheme, enabling the ADC to switch between SAR and NS-SAR modes. This approach reduces the power consumption of the comparator while maintaining NS functionality. Furthermore, to eliminate the need for an external high-speed clock to control SAR logic and NS operation, this work utilizes a fully asynchronous logic driven solely by a sample-and-hold clock. Implemented in standard 130-nm CMOS technology, this prototype ADC achieves a measured 81.54-dB SNDR (13.25-bit ENOB) in a 100-kHz bandwidth with an oversampling ratio (OSR) of 25.

This paper proposes an input range boosting technique for successive-approximation-register (SAR) analog-to-digital converters (ADC). By performing a pre-comparison and switching the DAC accordingly, the input range of a SAR ADC can be doubled with limited power and area overhead. This effectively improves the power efficiency by relaxing the noise requirement and improves the area efficiency by using less DAC capacitors. A prototype ADC is fabricated in 65 nm CMOS and occupies an area of 0.0033 mm2. It consumes$34.06\ \mu\mathrm{W}$at 10 MHz sampling rate from a 1 V supply. The measured SNDR is 62 dB for a 5 MHz bandwidth, resulting in a Walden figure of merit ($\text{FoM}_{W}$) of 3.28 fJ/conversion step.

This work presents a reconfigurable delay and redundancy technique, which relaxes the reference driver requirements for a charge-redistribution SAR ADC. By selectively adding delay to the most critical SAR cycle, the overall speed of the ADC is only slightly degraded, while the output impedance of the driver or the amount of decoupling capacitance can be reduced substantially. In a simulated 10-bit 10 MS/s SAR ADC prototype, the proposed technique reduces the decoupling capacitance by 16× while maintaining 59.2 dB SNDR and 71.2 dB SFDR at a power consumption of $32 \mu \mathrm{W}$. The estimated area is 0.002 mm2including decoupling capacitors.