Demo Data from EDBT 2026 / reviewers in the wild / expert
Jorge Carrillo
dblp:175/6260
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 2016
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Embedded and real-time systems · 56% Reconfigurable computing and FPGAs · 44% |
Topics — the 3 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Reconfigurable computing and FPGAs
FPGA SoC |
0.2 | 1 | 2016 | SDSoC: A Higher-level Programming Environment for Zynq SoC and Ultrascale+ MPSoC · FPGA 2016 |
Embedded and real-time systems › embedded hardware platform › MPSoC
heterogeneous MPSoC |
0.2 | 1 | 2016 | SDSoC: A Higher-level Programming Environment for Zynq SoC and Ultrascale+ MPSoC · FPGA 2016 |
Embedded and real-time systems › embedded hardware platform
system-on-chip platform |
0.1 | 1 | 2016 | SDSoC: A Higher-level Programming Environment for Zynq SoC and Ultrascale+ MPSoC · FPGA 2016 |
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2016 | SDSoC: A Higher-level Programming Environment for Zynq SoC and Ultrascale+ MPSoCabstractZynq-7000 All Programmable SoC and the new Zynq Ultrascale+ MPSoC provide proven alternatives to traditional domain-specific application SoCs and enable extensive system-level differentiation, integration and flexibility through hardware, software and I/O programmability. Vinod Kathail, Welson Sun, Yogesh Chobe, Tom Shui, Jorge Carrillo |
FPGA | 6 |