Prevalent lossy image compression schemes can be divided into: 1) explicit image compression (EIC), including traditional standards and neural end-to-end algorithms; 2) implicit image compression (IIC) based on implicit neural representations (INR). The former is encountering impasses of leveling off bitrate reduction at a cost of tremendous complexity while the latter suffers from excessive smoothing quality as well as lengthy decoder models. In this paper, we propose an innovative paradigm, which we dub Unicorn (Unified Neural Image Compression with One Nnumber Reconstruction). By conceptualizing the images as index-image pairs and learning the inherent distribution of pairs in a subtle neural network model, Unicorn can reconstruct a visually pleasing image from a randomly generated noise with only one index number. The neural model serves as the unified decoder of images while the noises and indexes corresponds to explicit representations. As a proof of concept, we propose an effective and efficient prototype of Unicorn based on latent diffusion models with tailored model designs. Quantitive and qualitative experimental results demonstrate that our prototype achieves significant bitrates reduction compared with EIC and IIC algorithms. More impressively, benefitting from the unified decoder, our compression ratio escalates as the quantity of images increases. We envision that more advanced model designs will endow Unicorn with greater potential in image compression. The code will be made publicly available upon publication.

Graphs are suitable for modeling interconnection networks when designing parallel computing systems such as multiprocessor systems. Multiprocessor systems can significantly increase computational speed and efficiency by distributing tasks among multiple processors and allowing them to work simultaneously. If some processors fail, it can indeed have a significant impact on the parallel processing capability of a multiprocessor system. Therefore, the diagnosability serves as a crucial parameter. It is unquestionable that an outstanding multiprocessor system exhibits robust fault diagnosis capability. Investigating the system’s interconnection network to determine its diagnosability is an essential step in designing highly reliable multiprocessor systems. In this paper, we construct a large network obtained by the strong product of paths and cycles, which is beneficial for a parallel computing system. We subsequently determine its diagnosability to be 5 under the PMC model. Additionally, it has some good properties and is suitable for designing multiprocessor systems.

Large-format single-photon avalanche diode (SPAD)-based direct time of flight (dToF) sensors are expected to be widely applied in future L5 full driving automation. However, the high-power in-pixel TDCs and the huge amount of data generated by multiframe histogram sampling impose limitations on the pixel format of SPAD-based dToF sensors. To tackle this challenge, we proposed the Computing-in-pixel Edge-aware Detection and Reconstruction (CEDAR) architecture. In this architecture, edge pixels are recognized by charge-domain convolution (CDC) computing, and noise pixels are eliminated by in-memory denoising (IMD). Only few TDCs in these edge pixels are activated, resulting in significant power and data savings. Afterward, the full-format image is reconstructed by a U-Net using the obtained depth information from these edge pixels. For the first time, we proposed a high-resolution 512 × 512 SPAD-based dToF sensor with a low power of 83.3 mW, a distance accuracy of 0.9 cm, and a frame rate of 60 fps. The high-resolution 3D image can be reconstructed by only 3.5% sparse edge pixels, achieving a PSNR of 35.2 dB. The CEDAR architecture can achieve 16× pixel format and image resolution improvement under the same constraint of power dissipation.

This work presents a 128×128 pixel array receiver based on single-photon avalanche diode (SPAD) for free space optical communication (FSOC). Each pixel incorporates an active quenching circuit and a delay-time-adjusting circuit to reduce the afterpulsing effect and the dead time. To address the challenge of high-speed transmission of massive data in a large-format SPAD array, a column-wise decoding circuit with reduced bus parasitic capacitance and voltage-sensitive discrimination is proposed, which significantly reduces the latency of data transmission. Additionally, the receiver includes cluster engines with highly parallelized computation capabilities for tracking the central addresses of a laser spot. The chip has been designed using a 130nm CMOS technology. Simulation results of the receiver indicate that a bit error rate (BER) of 3 × 10−4can be achieved at 500Mbps with a sensitivity of -41dBm, under random NRZOOK bitstreams. Furthermore, the chip demonstrates 100% accuracy in tracking the laser spot at a rate of 100kHz during 1000 transceiver simulations.

Graphs are suitable for modeling interconnection networks when designing parallel computing systems such as multiprocessor systems. Multiprocessor systems can significantly increase computational speed and efficiency by distributing tasks among multiple processors and allowing them to work simultaneously. If some processors fail, it can indeed have a significant impact on the parallel processing capability of a multiprocessor system. Therefore, the diagnosability serves as a crucial parameter. It is unquestionable that an outstanding multiprocessor system exhibits robust fault diagnosis capability. Investigating the system’s interconnection network to determine its diagnosability is an essential step in designing highly reliable multiprocessor systems. In this paper, we construct a large network obtained by the strong product of paths and cycles, which is beneficial for a parallel computing system. We subsequently determine its diagnosability to be 5 under the PMC model. Additionally, it has some good properties and is suitable for designing multiprocessor systems.