In recent years, Network-on-Chip (NoC) has gained increasing popularity as a promising solution for the challenging interconnection problem in multi-processor systems-on-chip (MPSoCs). However, the interest of adversaries to compromise such systems grew accordingly, mandating the integration of security measures into NoC designs.

The advent of hardware Trojans is posing an increasing threat on complex integrated circuits. Network-on-Chip, the established communication infrastructure for many core systems-on-chip, are growing in complexity. Integration of third-party components, which are increasingly becoming valuable targets, exposes the surface for attacks through the injection of hardware Trojans. In this paper, we address active attacks on NoCs, and focus on the integrity of transmitted data. Basically, we use network coding for the transmission of data in order to increase efficiency and robustness.

Current and future applications impose high demands on software-defined radio (SDR) platforms in terms of latency, reliability, and flexibility. This paper presents a heterogeneous SDR MPSoC with a hexagonal network-on-chip to address these issues. It features four data processing modules and a baseband processing engine for iterative multiple-input multiple-output (MIMO) receiving. Integrated memory controllers enable dynamic data flow mapping and application isolation. In a 4 x 4 MIMO application scenario, the MPSoC achieves a throughput of 232 Mbit/s with a latency of 20 μs while consuming 414 mW. It outperforms state-of-the-art platforms in terms of throughput by a factor of 4.

Rapid scaling of transistor gate sizes has significantly increased the density of on-chip integrations and paved the way for many-core systems-on-chip with highly improved performances. The design of the interconnection network of these complex systems is a critical one and the network-on-chip is now the accepted efficient interconnect for such large core arrays. An unfortunate adverse effect of technology scaling is the increased susceptibility to failures resulting in failing links and routers in the network-on-chip. To keep the network connected, efficient fault adaptive routing algorithms are necessary to route around faults. To design and evaluate the fault resiliency of such adaptive routing algorithms, fast, accurate and flexible analytic models are required, especially in large networks for which simulations are extremely time costly. In this paper, we present an analytic approach to evaluate the reliability of adaptive routing algorithms based on algebraic manipulations of the channel dependency matrix. It allows also to evaluate the number of alternate paths between source-destination pairs, in the presence of any number of permanent faults in the network. The analytic model is general and can be adapted to evaluate network reliability for any network topology and with any adaptive routing algorithm based on the turn model. We present cycle-accurate simulations to compare the accuracy of the model for the 2-D mesh and the hexagonal networks. The model is able to estimate the network fault resilience with an accuracy of about 1% and more than 70 times faster than the cycle accurate simulation.

This paper presents a heterogeneous database hardware accelerator MPSoC manufactured in 28 nm SLP CMOS. The 18 mm2 chip integrates a runtime task scheduling unit for energy-efficient query processing and hierarchical power management supported by an ultra-fast dynamic voltage and frequency scaling. Four processing elements, connected by a star-mesh network-on-chip, are accelerated by an instruction set extension tailored to fundamental data-intensive applications. We evaluate the MPSoC with typical database benchmarks focusing on scans and bitmap operations. When the processing elements operate on data stored in local memories, the chip consumes 250 mW and shows a 96x energy efficiency improvement compared to state-of-the-art platforms.

Technology scaling has allowed the integration of a large number of cores on a single chip, which significantly improves the speed of on-chip processing. Network-on-chip is the interconnection network which provides efficient and flexible communication between cores in such multi-processor systems-on-chip. However, the performance enhancements of technology scaling come at the cost of reliability as on-chip components particularly the network-on-chip become increasingly prone to faults. Redundancy is the basic approach to fault tolerance and in this paper we investigate the hexagonal on-chip network topology with redundant diagonal inter-router links, having approximately 1.5 times the number of links as the mesh topology. To evaluate the fault tolerance of the hexagonal network with wormhole-switched routing, we present deadlock-free fault tolerant routing algorithms obtained by applying the turn model and without the use of costly virtual channels. To circumvent the problem of finding the right selection of turns to prevent deadlock, we propose an approach based on the transitive closure of the channel dependency matrix. The results indicate that the hexagonal NoC with the proposed adaptive routing algorithms significantly improves NoC resilience by being able to tolerate two router faults, while the mesh NoC can tolerate only one router fault. Moreover, the proposed approach is general and can be adopted for developing adaptive routing algorithms for any regular network topology.

Due to technology scaling, the number of processor cores on a chip constantly increases. Already today, we reach the domain of so called many-core systems-on-chip. However, this advance comes at the cost of reliability, which especially affects the communication performance of the underlying network-on-chip. Today's resiliency concepts for network-on-chip like automatic repeat request with retransmission are not feasible anymore and lead to long latencies and high network load. In this paper, we propose an on-chip transmission concept based on random linear network coding to provide high resiliency and an efficient communication in many-core processors at the same time. The concept offers a flexible and efficient computable coding scheme, which is well suited for on-chip communication and allows to exploit the path diversity of large networks. First, we use a flit-level cycle-accurate simulation model to investigate the performance potential of the proposed transmission scheme on a network-on-chip with 64 cores. Second, we propose an analytic model for random linear network coding in network-on-chip with retransmission, which is able to provide a very accurate performance estimation close to the cycle-accurate simulation. Finally, we apply the analytic model to investigate the performance potential on the large-scale, assuming a processor with 1024 cores.