Modern engineering, spanning electrical, mechanical, aerospace, civil, and computer disciplines, stands as a cornerstone of human civilization and the foundation of our society. However, engineering design poses a fundamentally different challenge for large language models (LLMs) compared with traditional textbook-style problem solving or factual question answering. Although existing benchmarks have driven progress in areas such as language understanding, code synthesis, and scientific problem solving, real-world engineering design demands the synthesis of domain knowledge, navigation of complex trade-offs, and management of the tedious processes that consume much of practicing engineers' time. Despite these shared challenges across engineering disciplines, no benchmark currently captures the unique demands of engineering design work. In this work, we introduce EngDesign, an Engineering Design benchmark that evaluates LLMs' abilities to perform practical design tasks across nine engineering domains. Unlike existing benchmarks that focus on factual recall or question answering, EngDesign uniquely emphasizes LLMs' ability to synthesize domain knowledge, reason under constraints, and generate functional, objective-oriented engineering designs. Each task in EngDesign represents a real-world engineering design problem, accompanied by a detailed task description specifying design goals, constraints, and performance requirements. EngDesign pioneers a simulation-based evaluation paradigm that moves beyond textbook knowledge to assess genuine engineering design capabilities and shifts evaluation from static answer checking to dynamic, simulation-driven functional verification, marking a crucial step toward realizing the vision of engineering Artificial General Intelligence (AGI).

Sensors in mobile devices and IoT systems increasingly generate data that may contain private information of individuals. Generally, users of such systems are willing to share their data for public and personal benefit as long as their private information is not revealed. A fundamental challenge lies in designing systems and data processing techniques for obtaining meaningful information from sensor data, while maintaining the privacy of the data and individuals. In this work, we explore the feasibility of providing local differential privacy on ultra-low-power systems that power many sensor and IoT applications. We show that low resolution and fixed point nature of ultra-low-power implementations prevent privacy guarantees from being provided due to low quality noising. We present techniques, resampling and thresholding, to overcome this limitation. The techniques, along with a privacy budget control algorithm, are implemented in hardware to provide privacy guarantees with high integrity. We show that our hardware implementation, DP-Box, has low overhead and provides high utility, while guaranteeing local differential privacy, for a range of sensor/IoT benchmarks.

As the amount of digital data the world generates explodes, data centers and HPC systems that process this big data will require high bandwidth and high capacity main memory. Unfortunately, conventional memory technologies either provide high memory capacity (e.g., DDRx memory) or high bandwidth (GDDRx memory), but not both. Memory networks, which provide both high bandwidth and high capacity memory by connecting memory modules together via a network of pointto-point links, are promising future memory candidates for data centers and HPCs. In this paper, we perform the first exploration to understand the power characteristics of memory networks. We find idle I/O links to be the biggest power contributor in memory networks. Subsequently, we study idle I/O power in more detail. We evaluate well-known circuitlevel I/O power control mechanisms such as rapid on off, variable link width, and DVFS. We also adapt prior works on memory power management to memory networks. The adapted schemes together reduce I/O power by 32% and 21%, on average, for big and small networks, respectively. We also explore novel power management schemes specifically targeting memory networks, which yield another 29% and 17% average I/O power reduction for big and small networks, respectively.

A self-calibration technique was developed for SAR analog-to-digital converters that employ binary-weighted capacitors. High-accuracy calibration is achieved by finding and correcting the mismatch of each capacitor independently. The mismatch errors are extracted at power-up, and corrected by individual calibration DACs during the conversion. Unlike in previous schemes, in the proposed method the residual error in the calibration of a capacitor does not affect the calibration of any other capacitor. Simulation results show that the proposed method is also insensitive to the non-idealities of the calibration DACs.

This paper presents a technique for automated design and optimization of low-noise oscillators. A sensitivity analysis for oscillators guides the reduction of oscillator noise intensities and improvement of oscillator's immunity to noise. A design-oriented approach to circuit analysis efficiently handles design constraints and reduces the dimensionality of the optimization problem. The perturbation projection vector based phase noise computation makes the proposed optimization technique general and applicable to all types of oscillators, independent of circuit topology. Several examples illustrate the benefits of the new optimization approach.

A design-oriented periodic steady-state analysis is presented in this paper. The new analysis finds the values of circuit parameters that result in a desired circuit performance specified by a set of equality constraints. This is done by including the design equality constraints and the circuit parameters directly in the steady-state analysis as additional equations and unknowns. A time-domain finite difference method and the numerical implementation for the proposed analysis are described. Several examples demonstrate that the new analysis accurately and efficiently tunes circuit parameters that conform to a wide range of design specifications.

This paper presents an analysis for calculating sensitivities of an oscillator's periodic steady state and perturbation projection vector to design, process, or environmental parameters. A general continuous-time formulation and time-domain numerical methods are described. The applications of the oscillator sensitivity analysis in design optimization, macromodeling, as well as in analyzing the impact of process variations are demonstrated through examples.

This paper presents an analysis for calculating sensitivities of an oscillator’s periodic steady-state and perturbation projection vector to design, process, or environmental parameters. A general continuous- time formulation is described. Applications of the oscillator sensitivity analysis in design optimization and macromodeling are demonstrated through examples.

A method to generate stable transconductance (g/sub m/) without using precise external components is presented. The off-chip resistor in a conventional constant-g/sub m/ bias circuit is replaced with a variable on-chip resistor. A MOSFET biased in triode region is used as a variable resistor. The resistance of the MOSFET is tuned by a background tuning scheme to achieve the stable transconductance that is immune to process, voltage and temperature variation. The transconductance generated by the constant-g/sub m/ bias circuit designed in 0.18/spl mu/m CMOS process with 1.5F supply displays less than 1% variation for a 20% change in power supply voltage and less than /spl plusmn/1.5% variation for a 60/spl deg/C change in temperature. The whole circuit draws approximately 850/spl mu/A from a supply.