Keyword spotting (KWS) is an important task on edge low-power audio devices. A typical edge KWS system consists of a front-end feature extractor which outputs mel-scale frequency cepstral coefficients (MFCC) features followed by a back-end neural network classifier. KWS edge designs aim for the best power-performance-area metrics. This work proposes an area-efficient ultra-low-power time-domain infinite impulse response (IIR) filter-based feature extractor for a KWS system. It uses a serial architecture, and the architecture is further optimized for a low-cost computing structure and mixed-precision bit selection of the IIR coefficients while maintaining good KWS accuracy. Using a 65 nm process technology and a back-end neural network classifier, this simulated feature extractor has an area of 0.02 mm2and achieves$\mathbf{3.3}\mu \mathbf{W}$@ 1.2 V, and achieves 92.5% accuracy on a 10-keyword, 12-class KWS task using the GSCD dataset.

This paper presents a low-power and low-noise instrumentation amplifier (IA) for bio-impedance sensing ap-plications. To solve the loop gain reduction problem when the input resistor in a transconductance (TC) stage decreases as low as$< 10\mathrm{k}\Omega$, two positive-feedback-based gain boosting techniques are applied to the flipped voltage follower circuit: (1) a super gain casco de current mirror and (2) a current mirror amplifier with local positive feedback. Simulated in a 65 nm CMOS process, the designed IA ensures a 70 dB DC loop gain within the TC stage while achieving 40$\mathbf{nV}/\sqrt{\mathbf{Hz}}$input referred noise floor and a 369kHz bandwidth at 3.11$\mu \mathrm{W}$power consumption, 1 V supply. The enhanced loop gain leads to only a 0.04 dB (0.46%) IA gain deviation over the PVT variations.

Multi WLs Driving ➔ Low Energy Efficiency by ADC (<100 TOPS/W)

Current-efficient, fast-transient reconfigurable low-dropout regulator (LDO) is proposed for the wireless sensor network (WSN) system. The proposed LDO is designed and simulated in a 65 nm CMOS process showing the 3 key features: 1) a reconfigurable LDO architecture to achieve both low quiescent current (IQ) and wide bandwidth by adaptively adjusting to different load current conditions, 2) ultra-low-IQ and high PSR regulator for light-load efficient operation utilizing the gain boosting scheme within the flipped voltage follower loop, and 3) fast transient regulator for robust heavy-load operation with level-shifted impedance attenuation buffer (IAB) to reduce the supply ripples generated by wireless transceiver. The proposed LDO shows the state-of-the-art 93.8% current efficiency in the load condition of 1 μA, and achieves 0.672 ns response time even with 10 ns load transition.

An ultra-low-power analog-digital hybrid always-on face recognition (FR) processor integrated with a CMOS image sensor (CIS) is proposed for the wearable mobile devices applications such as user authentication. The proposed processor is the first IC with full process of FR in a single chip. The processor adopts analog-digital hybrid convolution operation for efficient integration of CNN processor with CIS. The analog convolution processor is proposed for the computation of the 1stlayer of CNN and the quantization operation without an ADC that can achieve 15.7% power reduction with 1.3% minimal accuracy loss. In addition, the analog weighted-sum unit with low power (5.18TOPS/W) is proposed with switched-drain regulation (SDR) current mirror which can achieve less than 6% mirroring error. The processor is simulated in 65-nm CMOS technology, 15.84mm2area with 2.5V and 1.2V for analog domain and 0.77-1.1V for digital domain. It consumes 0.6198mW to evaluate one face at 1 fps and achieves 96.18% FR accuracy in LFW dataset.

A dedicated ultra-low power arterial pulse wave (APW) sensor for wrist watch type system is implemented in 0.18-μm CMOS technology with 1.8-V supply. A duty cycle controlled (DCC) current source (CS) enables low-power consuming current injection with 98% power reduction. A DC balanced amplifier reduces settling time by 72%, enabling fast APW signal acquisition when motion artifact is occurred. The simulated 2.125-mm2 single chip APW sensor consumes only 54-μW.