This brief presents a time-domain method to optimize the phase-frequency detector (PFD) reset delay,$\tau _{reset}$, in charge-pump (CP) phase-locked loops (PLLs). In charge-pump PLLs (CP-PLLs), reducing$\tau _{reset}$generally lowers the reference spur and can improve jitter, but an excessively small$\tau _{reset}$causes the PFD dead-zone operation and degrades jitter. To narrow$\tau _{reset}$search space and identify its optimum, the proposed method uses a SystemVerilog (SV)-based PFD-CP behavioral model that represents current settling, charge sharing, charge injection, and clock feedthrough using piecewise exponential functions to reproduce the CP output-current waveform. Compared with a conventional phase-domain model, the proposed model predicts$\tau _{reset}$-dependent PLL behavior more accurately. At$\tau _{reset} = 100$ps, the jitter prediction error is reduced from 66.7% to 8.7%. In addition, the proposed reference-spur-based$\tau _{reset}$selection identifies the same optimum$\tau _{reset}$as the postlayout simulation. A 3.2-GHz prototype CP-PLL fabricated in 28-nm CMOS validates the proposed method and, at the optimized$\tau _{reset}$, achieves an rms jitter of 1.12 ps, a reference spur of −56.4 dBc, apower efficiency of 1.09 mW/GHz, and an FoM${}_{J}$of −233.6 dB.

A compact power-on-reset (POR) circuit with a configurable brown-out reset (BOR) function is presented. An integrated voltage reference (VR) circuit provides a constant bias voltage that facilitates voltage-triggered POR/BOR operation, reliably preventing POR signal generation when the ramping supply voltage (${V} _{\text {DD}}$) level is too low. Moreover, the proposed POR circuit features a fast, configurable POR/BOR operation owing to an inverter-based trip point detector (TPD), which triggers the reset signal with a programmable trip point. The prototype POR circuit achieves a POR level higher than 752 mV with a maximum POR delay of$16.4~\mu $s at a 0.8–1.2-V${V} _{\text {DD}}$, supporting a wide range of supply ramping time from$1~\mu $s to 1 s. In addition, the prototype detects brown-out events with a supply drop of 0.1–0.4 V, generating the BOR signal. Designed using a 28-nm CMOS process, the prototype has a compact active area of$995.3~\mu $m2and a quiescent current of 162–974 nA at a 1-V${V} _{\text {DD}}$.

This brief presents an energy-efficient transceiver supporting a 10-Gb/s/lane display link interface between the application processor (AP) integrated circuits (IC) and timing controller (TCON)-embedded source driver IC for mobile applications. An embedded clocking scheme is adopted to save clock distribution power, which also reduces the required number of off-chip I/O channels. A transmitter (TX) sends 20-Gb/s aggregate data through two differential data lanes, and a receiver recovers a 5-GHz half-rate clock. The TX employs a latch-less serializer using divided clocks in a staggered phase, achieving energy efficiency of 0.43 pJ/b/lane. In the RX, a hybrid clock and data recovery (CDR) tracks a half-data rate with a digital loop filter (DLF) and subsequently locks the frequency and phase with an analog loop filter (ALF). By deactivating the DLF and edge deserializer once a coarse frequency lock is acquired, the RX achieves an energy efficiency of 0.53 pJ/b/lane. The prototype transceiver, fabricated using a 28-nm CMOS technology, occupies an active area of 0.196 mm2 and achieves an energy efficiency of 1.23 pJ/b/lane, including a charge-pump phase-locked loop (CP-PLL) with clock distribution.

This article presents the design of an area/ power-efficient discrete-time (DT) delta-sigma ($\Delta \Sigma $) modulator suitable for multichannel sensor applications. First, the area efficiency of the modulator is achieved by optimizing the size of the sampling capacitor with the compact integrators based on the dynamic-boost inverter (DBI). The DBI is designed to have a small active area of only 0.00044 mm2, due to its self-bias scheme that eliminates the need for additional hardware for biasing circuitry. Second, the power efficiency is improved through the quantitative design approach to reduce the power consumption of the integrators by optimizing the gain–bandwidth product (GBW) of the DBI-based OTA in each integrator. In addition, the static current consumption of the integrators is further reduced due to the power-saving feature of the DBI utilizing the principle of a composite transistor. Finally, the self-bias scheme ensures that the DBI maintains a dc gain of 44.3 dB despite circuit mismatch by balancing the currents of the nMOS and pMOS transistors in the DBI. The prototype modulator, fabricated using 0.18-$\mu \text{m}$CMOS technology, occupies an active area of 0.0939 mm2. For a 25-kHz bandwidth (BW), the modulator achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 84.0 dB, a peak SNR of 85.1 dB, and a DR of 87.1 dB with a power supply rejection ratio (PSRR) of 56.8 dB and a common-mode rejection ratio (CMRR) of 66.1 dB at a 1.8-V supply. The modulator also maintains an SNDR higher than 82.5 dB and a DR higher than 85.5 dB for a 5–25-kHz BW with an${\mathrm {FoM}}_{W}$of 78.4–103.4 fJ/conversion at a 1.5–1.8-V supply.

This article presents a fully passive noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) that can be compatible with dynamic voltage and frequency scaling (DVFS) schemes while offering a 12-bit resolution for Internet-of-Things (IoT) sensor applications. To realize a voltage-scalable suppression of the in-band quantization noise, the proposed ADC utilizes a second-order cascade of integrators with feedforward (CIFF) NS loop with a 3-input dynamic comparator, which can obtain an additional resolution of more than 3 bits. A cyclic dynamic element matching (CDEM) for MSB is seamlessly combined with the NS operation and simply realized by shift registers (SRs). The MSB CDEM reduces dominant in-band harmonic distortions due to capacitor mismatch by not only averaging out but also randomizing the MSB mismatch errors with modulation dither from the CIFF NS loop. In addition, a last-bit majority voting (LMV) technique is applied when resolving the LSB to reduce the comparator noise by half with four additional cycles. With both the LMV and CDEM techniques enabled, the SNR and SNDR are enhanced to 73.3 and 72.3 dB, respectively. The ADC achieves an ENOB of$11.2-11.7$bits with a reconfigurable bandwidth of 10–50 kHz at a supply voltage of 0.6–1 V. The prototype ADC was fabricated using 28-nm CMOS technology, occupying an active area of 0.0575 mm2.

A novel self-capacitance transition sensing method is presented for low-power touch detection using a capacitive touch-screen. While maintaining a voltage level, an additional electric charge is additionally required when a touch-input is newly added; the amount of charge is used for detection. Accordingly, the proposed current mirroring voltage-level regulation (CM-VLR) circuit senses the transition of self-capacitance of the touch-screen and detects motions of the touch-object. Only one CM-VLR cell is used to scan the entire touch-screen. Thus low-power readout and high integrated-circuit area efficiency are achieved. Moreover, the proposed self-capacitance sensing method does not require an offset-calibration step through a charge-sharing-based voltage generation and the offset-coverage capacitor. Fabricated in a 180-nm CMOS process, and the CM-VLR cell occupies 0.12 mm2. At a 120-Hz report rate, the proposed analog front-end (AFE) detects touch-input at a 32-dB SNR while dissipating 2.1 mW.