This article presents an all-digital 6T-SRAM-based compute-in-memory (D6CIM) macro that supports 1-to-8-bit fixed-point vector matrix multiplication. The D6CIM is fully digital, employing only digital standard cells and 6T SRAM bitcells. The D6CIM adopts a time-sharing architecture with an optimal degree of time-sharing to maximize the product of compute density and weight density. It also features several circuit techniques, namely non-precharge single-ended access, hybrid compressor adder-tree circuits, and bidirectional shift-accumulation. We prototype the D6CIM macro in a 28-nm CMOS technology. The maximum operating frequency is ~360 MHz in a 1.1-V supply. The energy efficiency is measured at up to 60.4 TOPS/W. It achieves a compute density of 1.46 TOPS/mm2and a weight density of 1005 kb/mm2. Compared to prior state-of-the-art CIM macros, the D6CIM achieves 1.3-4.8X improvement in the product of energy efficiency, compute density, and weight density.

This brief presents an energy-efficient transceiver supporting a 10-Gb/s/lane display link interface between the application processor (AP) integrated circuits (IC) and timing controller (TCON)-embedded source driver IC for mobile applications. An embedded clocking scheme is adopted to save clock distribution power, which also reduces the required number of off-chip I/O channels. A transmitter (TX) sends 20-Gb/s aggregate data through two differential data lanes, and a receiver recovers a 5-GHz half-rate clock. The TX employs a latch-less serializer using divided clocks in a staggered phase, achieving energy efficiency of 0.43 pJ/b/lane. In the RX, a hybrid clock and data recovery (CDR) tracks a half-data rate with a digital loop filter (DLF) and subsequently locks the frequency and phase with an analog loop filter (ALF). By deactivating the DLF and edge deserializer once a coarse frequency lock is acquired, the RX achieves an energy efficiency of 0.53 pJ/b/lane. The prototype transceiver, fabricated using a 28-nm CMOS technology, occupies an active area of 0.196 mm2 and achieves an energy efficiency of 1.23 pJ/b/lane, including a charge-pump phase-locked loop (CP-PLL) with clock distribution.

A digital low dropout (DLDO) regulator is one of the most critical building blocks in on-chip power management for its technology portability, voltage scalability, and other benefits associated with digital-oriented design. A key metric of DLDOs is the dynamic load regulation performance, often measured as the maximum current that a DLDO can quickly supply upon a significant load step under a voltage droop constraint (usually 10% of the output voltage). Previous works focused on architecture and circuit techniques to improve this metric. However, limited research focuses on the model development for the dynamic load regulation performance. To fill this gap, in this article, we propose the analytical models of the maximum load current of the standard DLDOs employing feedback and feedforward control laws. The developed models shed light on the impact of various design parameters on the total load current of a DLDO, with which both circuit and system designers can navigate the design space quickly and effectively.

A novel self-capacitance transition sensing method is presented for low-power touch detection using a capacitive touch-screen. While maintaining a voltage level, an additional electric charge is additionally required when a touch-input is newly added; the amount of charge is used for detection. Accordingly, the proposed current mirroring voltage-level regulation (CM-VLR) circuit senses the transition of self-capacitance of the touch-screen and detects motions of the touch-object. Only one CM-VLR cell is used to scan the entire touch-screen. Thus low-power readout and high integrated-circuit area efficiency are achieved. Moreover, the proposed self-capacitance sensing method does not require an offset-calibration step through a charge-sharing-based voltage generation and the offset-coverage capacitor. Fabricated in a 180-nm CMOS process, and the CM-VLR cell occupies 0.12 mm2. At a 120-Hz report rate, the proposed analog front-end (AFE) detects touch-input at a 32-dB SNR while dissipating 2.1 mW.

We propose a novel control framework to enable nonholonomic wheeled mobile robots (WMRs) to autonomously drive in an environment with the speed fast enough so that the dynamics effect (e.g., Coriolis effect) is not negligible, yet, still less than a certain threshold to prevent slippage at the wheels. For this, instead of the Newtonian vehicle modeling, we adopt Lagrange-D'Alembert formulation, which then allows us to explicitly relate the system's state/control with the constraint force, so that we can predict/detect possibility of a given motion's violating the no-slip condition. We present a scheme to generate a no-slip/collision-free timed-trajectory for the WMRs using this Lagrange-D'Alembert formulation. We also propose a backstepping-based control law, which enables the WMR to track the generated trajectory while respecting its nonholonomic constraints. Experiment, using a modified commercial radio-controlled car, is performed to verify the theory.