Approximate multiplier saves energy and improves hardware performance for error-tolerant computation-intensive applications. This work proposes hardware-efficient FPGA-based approximate multipliers with look-up table (LUT) sharing and carry switching. Sharing two LUTs with the same inputs enables to fully utilize the available LUT resources. To mitigate the accuracy loss incurred from this approach, the truncated carry is partially reserved by switching it to the adjacent calculation. In addition, we create a library of 8×8 approximate multipliers to provide various multiplication choices. The proposed design can provide enhancements of up to 38.75% in power, 17.29% in latency, and 28.17% in area compared to the Xilinx exact multiplier. Our proposed designs are open-source at https://github.com/YnuGuoLab/DATE_FPGA_Approx_Mul and assist in further reproducing and development.

Approximate computing has become an emerging technique to reduce power consumption. In numerous applications, multiplication is a crucial operation, designing it for approximation is effective in optimizing system performance. In this paper, we propose low-power FPGA-based multipliers by employing the novel compressor designs. Given that the compressor is the primary unit in the multiplier, we introduce novel exact and approximate compressors with low-complexity circuits to parallelly accumulate the elements. To flexibly configure the proposed compressors, a compressor-based once-through structure is proposed to 8×8 multipliers. Two variants of the approximate multipliers are provided with different accuracy-hardware trade-offs. Compared with the exact multiplier, the proposed approximate multiplier reduces power by 57.90%, area by 33.80%, and delay by 24.78%. With a similar accuracy loss, the proposed designs save more hardware resources than others. In addition, the effectiveness of approximate multipliers is assessed in image sharpening.

Intelligent factories driven by deep vision technology use robotic arms to perform tasks such as picking and assembling in a production environment. In practical applications, with the continuous changes of products on the industrial pipeline, the detection model needs to continuously train new weights to adapt to new application scenarios. It is time-consuming and labor-intensive to manually collect training data when deploying the production line, and it cannot be quickly adapted in industrial scenarios. Therefore, we propose an attention RPN (Region Proposal Network) few-shot object detection algorithm based on geometric prior. The algorithm uses the attention RPN module to strengthen the feature extraction ability of the detection model and uses the virtual simulation software to generate synthetic data similar to the real object geometry as the base class data to train the feature extraction network so that the network obtains the ability to extract geometric features on the base class object. By comparing the learning strategies, only a small number of real data samples are used to train the detection model twice. The experimental results show that the algorithm can detect more objects than the existing few-shot object detection algorithm in the industrial scene with only a small amount of real sample data, and the detection accuracy can reach 97%.

In light of burgeoning technological progress and burgeoning labor deficits, the adoption of industrial robots has markedly intensified. These sophisticated automatons are pivotal in addressing the growing trend of high-mix, low-volume production, catering to the heterogeneous requisites of end-users. In this domain, it is imperative for industrial robots to facilitate automated bin picking, ensuring versatility and continuity in production workflows. Despite this, extant bin picking modalities fall short in discerning and orienting designated parts accurately. Our study introduces an avant-garde 3D object recognition framework, underpinned by deep learning algorithms, to streamline the bin picking process, obviating the necessity for human intervention. Moreover, while annotated data remains the cornerstone of deep learning paradigms, its procurement through conventional annotation is fraught with challenges. Addressing this bottleneck, we put forth a strategy that exploits training data autonomously generated within a simulation milieu, laying the groundwork for an object recognition model that eschews manual calibration. This model adeptly harnesses both bi-dimensional imagery and tri-dimensional point clouds to refine its recognition capabilities. Our empirical investigation, straddling simulated and authentic settings, substantiates the precision of our proposed methodology.

Approximate multipliers enable hardware savings for error-resilient computation-intensive applications. Most existing approximate multipliers have been on ASIC-based circuits. They might not achieve comparable performance gains when used for FPGA-based accelerators. In this paper, we propose hardware-efficient FPGA-based accurate and approximate$4\boldsymbol {\times }4$multipliers with novel methodologies of look-up table (LUT) sharing and carry switching. The LUT resources can be fully utilized by sharing two LUTs with the same inputs. To compensate for the accuracy loss, the truncated carry is partially reserved by switching it to the adjacent calculation. For higher-order multipliers, three approximate adders are proposed to sum the result of the multipliers with arbitrary size. 140 types of$8\boldsymbol {\times }8$multipliers are constructed by combining the proposed$4\boldsymbol {\times }4$multipliers and adders, providing various multiplication choices for different demands. The proposed approximate$8\boldsymbol {\times }8$multiplier can achieve up to 38.75%, 17.29%, and 28.17% improvements in power, latency, and area over the Xilinx exact multiplier, respectively. Moreover, the proposed accurate and approximate$8\boldsymbol {\times }8$multipliers with different adders are extended to$16\boldsymbol {\times }16$multipliers. As evidenced by the performance of the$16\boldsymbol {\times }16$multipliers, our methodology demonstrates the capability to design higher-order multipliers flexibly. Compared with previous works under a similar accuracy loss, the proposed multiplier achieves more hardware savings. Furthermore, the approximate multipliers are assessed on the application of image processing to validate the practical applicability. We create a library of the proposed multipliers which is open-source athttps://github.com/YnuGuoLab/Approx_Mul_FPGA/and assist in further reproducing and development.

To satisfy the development trend of a few workers or unmanned production in industries, especially in dangerous mining industry, the safety patrol robot is required to replace the safety inspectors. The challenge is how to model the cognition mechanism of inspectors for the safety patrol. The specific problems involve the cognition modeling scheme, the aliasing of the commonly used empirical mode decomposition (EMD) of the electroencephalograph (EEG) filtering, the multisource EEG feature vector construction, and the brain-inspired modeling method. To this end, this article focuses on the perception feature and cognition model applied to safety patrol robot in mining industry. First, the inspector's cognition modeling scheme is designed by using brain-computer interface. Second, a filtering algorithm is developed by embedding the sample entropy and independent component into the EMD. Third, a multisource EEG feature vector is fused by using the power spectral density and the EEG map and the functional brain connectivity. Fourth, the cognition model is built by a convolutional neural network embedded the inception module. The experiments indicate that the modeling scheme is effective. The developed filtering algorithm increases the signal-to-noise ratio by 4.16%. The integrated model reaches the average accuracy of 88.17%.