This brief proposes an average-6.5T twin cell for a deep sub-micrometer 64kb SRAM, which utilizes two identical asymmetric single-ended (SE) 6T cells in a column with a shared read assist device to improve read margin and write ability. It enables the SRAM to achieve read-disturb-free, near/sub-threshold operation and compact array layout, resulting in area and energy efficiencies. The average-6.5T SRAM test chip is fabricated using a 65 nm CMOS logic process. Its cell area shows only 5.6% overhead compared to the standard 6T cell, and is smaller than that of other low-voltage SRAMs. Measured full read and write functionality is performed with VDD down to 0.39 V, which is lower than that of standard 6T and 8T SRAMs. In addition, its minimum energy point of 6.3 pJ is obtained at 0.48 V.

Software testing is a critical component in software development that is closely related to software quality. Traditional test generation methods face challenges such as producing test cases that are difficult to read and maintain synchronously. Meanwhile, with the advancement of large language models (LLMs) in code generation, the quality of LLM-generated code is increasingly comparable to human-written code. Therefore, this paper proposes a test code generation framework using Model-driven Multiple Results Filtering and Multi-Round Generation strategy (Model-MRFaG). To better adapt to test generation tasks for mainstream programming languages, we built an Alpaca-format Test-Code DataSet for Finetuning Baseline Models (TCDSF) containing six programming languages: Python, Java, JavaScript, C++, C#, and Go, and used this dataset to fine-tune a Baseline Model to obtain the TestCoder model. Subsequently, we developed the Model-MRFaG framework based on the TestCoder model to further improve the accuracy of test code generation. Through comparative experiments evaluating both general test sets and test code generation capabilities, TestCoder outperforms the Baseline Model in both general test sets and test code generation accuracy. Furthermore, the Model-MRFaG framework can further improve the accuracy of test code generation, providing a new solution approach for the intelligent development of software testing.

The novel nonvolatile computing-in-memory (nvCIM) technology enables data to be stored and processed in situ, providing a feasible solution for the widespread deployment of machine learning algorithms in edge AI devices. However, current nvCIM approaches based on weighted current summation face challenges such as device nonidealities and substantial time, storage, and energy overheads when handling high-precision analog signals. To address these issues, we propose a resistive random access memory (RRAM)-based binary convolution macro for constructing a complete binary convolutional neural network (BCNN) hardware circuit, accelerating edge AI applications with low-weight precision. This macro performs error compensation at the circuit level and provides stable rail-to-rail output, eliminating the need for any ADCs or processor to perform auxiliary computations. Experimental results demonstrate that the proposed BCNN full-hardware computing system achieves on-chip recognition accuracy of 90.7% (98.64%) on the CIFAR10 (MNIST) dataset, which represents a decrease of 0.98% (0.59%) compared to software recognition accuracy. In addition, this binary convolution macro achieves a maximum throughput of 320 GOPS and a peak energy efficiency of 578 TOPS/W at 136 MHz.

Security and cost efficiency are of utmost importance for embedded processors when it comes to limiting hardware resources in IoT applications. This brief presents a security reduced instruction set computer-five (RISC-V) specific instruction set extension (ISE) designed based on hardware-assisted orthogonal obfuscation for hardware security. The orthogonal obfuscation defines an architecture geared toward high-security processors that supports a Pay-Per-ISE function using a key management unit (KMU), thus capable of supporting the customization of the key for a user’s partially authorized ISE and controlling the unlocking of the specific ISE. The proposed security RISC-V test chip is fabricated in a 65-nm CMOS technology with a core area occupying about 0.739 mm2. The measured results demonstrate that our processor realizes the instruction set authorization function. The results show an average power of 52.8 mW at 1.2 V, a hardware overhead of <3% at 50 MHz, and a 30% improvement in security.

This paper presents an oil painting authentication scheme based on physical unclonable function (PUF), aiming to address the high cost and cumbersome process associated with existing oil painting authentication technology. The proposed technique utilizes oil painting texture deviation to generate highly secure PUF information, serving as the digital fingerprint of the oil painting for authentication. The captured oil painting image is first preprocessed using histogram equalization technology to mitigate the influence of light intensity in the shooting environment. Subsequently, the feature extraction model based on local binary pattern (LBP) calculates the preprocessed image, yielding a sequence of 130 feature values containing unique information about oil painting texture deviation. A PUF key algorithm is then designed to map the feature value sequence into a 128-bit binary PUF key, uniquely corresponding to a specific oil painting. Furthermore, a PUF-based oil painting authentication protocol is constructed to provide standardized and credible authentication for the art market. Finally, the security and reliability of the PUF key are analyzed. Experimental results demonstrate that the uniqueness of the proposed PUF is 50.03%. Additionally, PUF data successfully passes the NIST random number test, fully proving its excellent randomness.

Traffic prediction methods on a single-source data have achieved excellent results in recent years, especially the Graph Convolutional Networks (GCN) based models with spatio-temporal dependency. In reality, various modes of urban transportation operate simultaneously. They influence and complement each other in common space-time occasions, constituting the transportation system dynamically. Thus, traffic data from multiple sources is ostensibly heterogeneous, but internally correlated. The typical single data driven models are, however, not universally applicable for heterogeneous traffic data. To address this issue, we propose a Multi-task Hypergraph Convolutional Neural Network (MT-HGCN) for the multi-source traffic prediction problem. The framework consists of a main task and a related task. Both tasks are based on Hypergraph Convolutional Neural Networks (HGCN) and are devoted to two prediction problems. Furthermore, the tasks are bridged by a feature compress unit, which models the correlation and shares the latent feature to improve the performance of the main task. The node-level forecasting has been evaluated on historical datasets of Beijing to verify the effectiveness of the proposed method. Compared with the state-of-the-arts, the superior performance of the proposed method can be obtained.

Analyzing the traffic state of large citywide networks is an inherently difficult task. Various data issues, traffic signals, stops signs and other flow inhibitors of the network-level traffic state make the analysis more difficult than that under the small-scale local traffic state. To address this challenge, we propose a method based on spatio-temporal non-negative matrix factorization (ST-NMF), which is used for road network traffic pattern analysis. The method can be further extended to traffic data reconstruction and traffic prediction. In order to analyze traffic patterns, the proposed spatio-temporal non-negative matrix factorization model represents the network traffic as a linear combination of several basic patterns, which is also interpreted as the dynamics of spatial traffic characteristics over time in low-dimensional space. By the visual display of the spatial and temporal patterns and the assistance of clustering methods, the traffic pattern features are extracted. In the extended applications, data reconstruction relies on the sampling representation of missing data by ST-NMF, and data prediction is based on the prediction of the temporal patterns by ST-NMF. Through our method, we can not only obtain a high-quality data foundation, but also explore typical spatio-temporal patterns and general predictions of the future traffic state. The analysis results have important guiding significance on the management of intelligent transportation systems. Experiments on real-world traffic data are provided to verify the validity of our proposed approach.