Logic diagnosis is essential for improving reliability and yield. In conventional diagnosis methods, although various methods are proposed to enhance the accuracy and resolution of logic diagnosis, there are still diagnosis results where the reported locations of defects are incorrect. Particularly in logic circuits, which contain a large number of gates, multiple faults can occur, not just single faults. Since the number of possible cases for multiple faults is significantly greater compared to single faults, the diagnosis of multiple faults is complicated. To address this problem, a new diagnosis method that uses a multistage process with fault candidate reduction is proposed. In the proposed method, machine learning is used with fault candidate reduction, and post-processing is performed after the use of machine learning. This proposed method allows for the analysis of multiple faults using only the test responses for single faults, demonstrating that this method can maintain sufficient accuracy and resolution for unexpected faults.

This article proposes a hybrid test scheme based on interleaved test applications to increase the efficiency of multisite testing of integrated circuits (ICs) by solving problems related to test coverage, which is an important feature in automotive IC, and test costs, including the number of test pins and the volume of test data. To solve the problems, a hybrid test scheme that combines the merits of broadcast-based scan compression and built-in self-test (BIST) is proposed. The proposed scheme not only generates deterministic test patterns, similar to scan compression, but also requires fewer test pins, similar to BIST, thereby increasing the efficiency of multisite testing. With appropriately designed linear-feedback shift registers (LFSRs) and seeds periodically inserted through the reduced test pins, the test application process combines deterministic testing and random testing. The random testing stage can compensate the seed-insertion time for the subsequent deterministic testing stage and reduce the number of required deterministic patterns by detecting easy-to-detect faults. For further reduction of the volume of test data and hardware overhead, some compatible scan chains (SCs) are grouped and receive test data from an LFSR. The experimental results show that the proposed method increases the efficiency of multisite testing with a reduced pin count.

The use of through silicon vias (TSVs) is essential for vertically connecting the individual circuit layers of a 3-D IC. However, because the pitch between TSVs is being decreased, it becomes more vulnerable to bridge defects between the TSVs. In the previous architectures, the parallel topology between the power supply and the bridge defects reduces the resolution of the test results and makes them very sensitive to process variations. In this article, an enhanced postbond test architecture that improves the testability of bridge defects screening with a floating control circuit of supply voltage driver is proposed. The proposed structure allows the selective formation of a series circuit that includes the supply voltage driver and bridge defects between the TSVs; the structure can improve the output voltage resolution of the bridge defects by 27.2 times over that of the previous architectures. According to the experimental results, while exhibiting a proper test time, hardware overhead, and peak current consumption for mass production, the system guarantees testability for the detection of bridge defects. Moreover, the Monte Carlo simulation results show that the proposed architecture has a higher test reliability under process variations than the current test architectures.

Invasive attacks, such as microprobing or focused-ion-beam (FIB) circuit editing are serious threats to security-related semiconductors. To ensure that there is security against invasive attacks, an effective countermeasure is to use a protective layer as a secure shield. Previous secure shield methods can be classified into one of two categories; detection circuits based on the delay difference or block ciphers. For the former, timing asymmetries caused by the capacitance of the probe are detected. The main drawback of this method is that it is highly vulnerable to chip editing by FIB equipment. FIB circuit editing can easily cripple the detection circuits of the secure shield. In contrast, the cryptographically secure shield based on the block cipher can provide strong protection against FIB circuit editing. However, it is prone to microprobing attacks because of its inability to detect the capacitance load of the probe. In this article, we propose a robust secure shield architecture against invasive attacks, including both probe attempts and the FIB circuit editing. The proposed method is based on the detection circuits with low hardware overhead and fast-analysis time and includes protection circuits to prevent information from being leaked.

After the 3-D stacking, 3-D-ICs based on through-silicon-vias (TSVs) must be inspected for any TSV defects such as resistive open or bridge defects. In some research studies, several effective testing techniques have been developed such as parallel or serial test architectures, which measure the voltage across a single TSV with a comparator. However, in the current test architectures, hardware overhead and test time are proportional to the number of TSVs. In this paper, we propose a new unified test architecture for screening of TSV defects in 3-D-ICs. Depending on the number of assembled TSVs, the proposed grouping-based test architecture can effectively reduce the cumulative test time and hardware overhead without compromising the test quality.

As a scan-based testing enables higher test coverage and faster test time than alternative ways, it is widely used by most system-on-chip (SoC) designers. However, since the number of logic gates is over one hundred million gates, a number of scan cells lead to excessive power consumption and it produces a low shifting frequency during the scan shifting mode. In this paper, we present a new scan shift power reduction method based on a scan chain reordering (SR)-aware X-filling and a stitching method. There is no need to require an additional logic for reducing the scan shift power, just a little routing overhead. Experimental results show that this method improves scan shift power consumption on benchmark circuits in most cases compared to the results of the previous works.