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Richard Brent

dblp:177/1264 · DBLP profile ↗
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2ranked-venue papers
2as first author
0since 2021 · last 1973
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Parallel and multicore computing · 60% Processor architecture and microarchitecture · 40%
Software engineering, system software, and programming languages
1 paper
Compilers and program optimization · 100%
Theoretical computer science
1 paper
Algorithms and data structures · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Compilers and program optimization
instruction scheduling		 0.011973
The Parallel Evaluation of Arithmetic Expressions Without Division · IEEE Trans. Computers 1973
Parallel and multicore computing › parallel algorithms › parallel symbolic computation
parallel expression evaluation		 0.011973
The Parallel Evaluation of Arithmetic Expressions Without Division · IEEE Trans. Computers 1973
Processor architecture and microarchitecture › computer arithmetic
binary addition		 0.011970
On the Addition of Binary Numbers · IEEE Trans. Computers 1970
Algorithms and data structures › parallel algorithms
parallel addition		 0.011970
On the Addition of Binary Numbers · IEEE Trans. Computers 1970

Methods — techniques the papers use, named apart from their topics

arithmetic expression analysis · 0.0circuit complexity analysis · 0.0
YearPublicationVenuePosition
1973 The Parallel Evaluation of Arithmetic Expressions Without Division
abstract
As computers become capable of executing more arithmetic operations simultaneously, the question of compiling for such machines becomes more important.
Richard Brent, Daniel Kuck, Kiyoshi Maruyama
 IEEE Trans. Computers1
1970 On the Addition of Binary Numbers
abstract
An upper bound is derived for the time required to add numbers modulo 2n, using circuit elements with a limited fan-in and unit delay, and assuming that all numbers have the usual binary encoding. The upper bound is within a factor (1 + ε) of Winograd's lower bound (which holds for all encodings), where ε→0 as n→∞, and only O(n log n) circuit elements are required.
Richard Brent
 IEEE Trans. Computers1