Next-generation sequencing deals with exponential growth in sequence databases; the primary challenge is aligning short-read sequences in a time-efficient manner. Despite numerous efforts in contemporary research, they unfortunately face trade-off issues related to time, power consumption, and resource constraints. A hardware accelerator is presented utilizing the Burrows-Wheeler Transformation without involving any sequence terminator to perform short-read sequencing at hardware speed, which eases additional storage, operations, and power consumption. Further, a hardware-based binary search scheme is introduced to reduce power consumption of the accelerator. As an alternative, a parallel searching mechanism is introduced to accomplish the searching operation in a single clock-cycle. The accelerator is evaluated for 64-to-256 nucleotide reference sequences and 32-to-56 nucleotide query sequences. The parallel search scheme consumes ≈11% less time than the binary search-based scheme, consuming ≈1.6–3.7% and ≈4.5–23% more resources and power. While comparing the accelerator with the with-terminator method, it achieves ≈31.01–33.13% gain in processing time, ≈31.28–34.47% saving in hardware resource, ≈33.08–33.29% saving in storage, and ≈14.03–50.79% gain in power consumption. Finally, this accelerator exhibits a gain of ≈52× in throughput without involving any terminator and external memory compared to state-of-the-art architectures.

Due to the exponential growth of sequence databases, the processing of genome sequencing in real-time is a fundamental problem. Though several schemes have been developed over the years, unfortunately, they suffer from time-consumption, power-consumption, and resource-bound trade-off issues. Another major issue concerns designing efficient architecture to perform the alignment of multiple sequences. A novel hierarchical multiprocessing architecture, designed around pipelined processing elements, is presented for multiple pair-wise sequence alignment at hardware-speed. In addition to parallel intra-sequence trace-back value generation, it can efficiently perform parallel inter-sequence computation to attain maximum utilization of processing elements. It can accomplish parallel trace-back operations to achieve massive parallelism. It consumes O(ni) or O(ji) clock-cycles to perform alignment operations for j-nucleotide query and i reference sequences of n-nucleotide, instead of O((n+j)i) or O(nji) clock-cycles used in state-of-the-art architectures. The entire architecture is evaluated for 16-to-512 multiple sequences of 16-to-512 nucleotides. It achieves ≈1.6 to ≈24 GCUPS (GCUPS: Giga Cell Updates Per Second) throughput and ≈5 to ≈12.5 GCUPS/W power-efficiency for 16-to-64 sequences and ≈1.6 to ≈5.6 GCUPS/W for 128-to-512 sequences. The peak throughput for 1024-nucleotide sequence is 128 GCUPS, and power-efficiency is 41 GCUPS/W. Finally, the presented architecture exhibits a gain of ≈2× in throughput and ≈6× in power-efficiency compared to state-of-the-art architectures.

A novel hardware architecture for Burrows-Wheeler Transform (BWT) scheme is presented. The core idea is to have a memory-free strategy that does not involve any software overhead during BWT operation. This is achieved by introducing a register-file concept and utilizing basic digital logic circuits to perform the entire BWT operation. Additionally, this is a kind of transformation scheme that does not utilize any kind of matrix during transformation, and thereby, it is free from run-time memory consumption. It efficiently handles the string terminating mechanism in the proposed design without involving any extra terminating symbol. This string terminator-free architecture eventually reduces additional operation and storage space to maintain the string, and thereby, the architecture does not necessitate any register read and write operations. This architecture exhibits efficient transformation without involving any indexing method or sorting mechanism during an inverse transformation operation. This architecture achieves$O(N)$time complexity compared to$O(N^{2})$and$O(N \log N)$as experienced by the existing state-of-the-art approaches.

This article presents a novel parallel comparison-free hardware sorting architecture that sorts$N$,$n$-bit elements consuming linear worst-case sorting latency of$\mathit {O(N)}$clock-cycles utilizing$k$-parallel clusters. A parallel cluster contains a number of identical blocks utilizing a few fundamental logic components. The architecture achieves a speed-up of${}({n}/[{\lceil {({n}/{k})}\rceil +k}])$over nonparallel architectures. The proposed sorting architecture identifies the largest element in every cycle with smaller clock periods compared to state-of-the-art comparison-free approaches and does not require any kind of preprocessing of the input data set, unlike most of the existing hardware sorters. The experimental result shows the degree of parallelism$(k)$for 16, 32, and 64-bit elements are, respectively, {4}, {4, 5, 6, 7, 8}, and {8} to achieve maximum system throughput. This sorter achieves a throughput of ≈194 Million Elements per second (MEps) for$k=6$and, it is ≈142 MEps for$k=8$to sort 256 elements of 32 and 64-bit, respectively, whereas it is ≈159 MEps for$k = 6$to sort 512 elements of 40 bit.

A novel hash-based hardware architecture for longest prefix match (LPM) scheme has been presented for IP processing.The main idea is to have zero false positive (+ve) rate with negligible false negative (-ve) rate. This has been achieved by implementing hardware-based simple hash functions for faster generation of routing table addresses. Prefix table has been designed using multiple read-port memory modules to deploy concurrent access of multiple memory words. Moreover, in this architecture, memory requirement has been reduced by maintaining next-hop address pointers instead of keeping actual next-hop address using global next-hop address memory. Prefix search time is fixed and restricts an LPM search operation within a single clock cycle irrespective of IPv4 and IPv6 address suits. This architecture can accommodate increased prefix growth trend of 40% – 100% with unchanged memory capacity. After rigorous testing, false -ve rate is found mostly zero and reasonably negligible (0.00512%) in worst-cases, however, false +ve rate is always zero. Lower bounds in memory requirements for four numerous schemes of the proposed LPM architecture with their probable failure-rates are analysed. System failure-rates are observed against incremental prefix growth with variable number of hash functions ranging from 6 to 8 to ensure future sustainability of the scheme.

This article proposes a novel comparison-free hardware sorting engine that sorts$N$unique$n$-bit elements (irrespective of signed and unsigned) consuming linear sorting latency of$O(N)$clock cycles. It can even efficiently sort$N$data elements with a nonzero duplicity rate in less than$O(N)$clock cycles. This sorting engine is designed using$n$-symmetric cascaded blocks utilizing few fundamental logic components. The entire design is synthesized for several data sets from pseudorandomly generated data elements to unique elements, and also from random to completely sorted elements with various duplicity rates. The architecture appears impartial with respect to ordering of elements. Synthesis results indicate that the proposed approach consumes reasonably lower field programmable gate array resources than existing approaches. The architecture takes per-element sorting latency in sorting 512 unique signed elements as 22.56 ns (48 bit) and takes 26.80 ns (64 bit) to sort 256 unique signed elements. The engine achieves sorting throughput rates as$\approx 117$-to-142 Million-Elements-per-second (MEps) (16 bit), 79-to-97 MEps (24 bit) for sorting 256-to-1K, whereas 66-to-73 MEps (32 bit) and 44-to-49 MEps (48 bit) for sorting 256-to-512 elements. However, it is 37 MEps (64 bit) in sorting 256 signed elements. This architecture consumes$\approx 1.52~\mu \text{W}$for the unique signed numbers (SNs) as per-byte processing power and$\approx 1.55~\mu \text{W}$for the SNs with nonzero duplicity rates.

Biological sequence alignment procedure demands an accurate, high speed, and efficient system to align sequences due to exponential growth of genomic databases. Several software-based as well as hardware-based schemes have been developed to perform alignment operation. Unfortunately, these approaches do not meet the requirement of hardware resource and processing time of recent growth of biological sequences. This article presents a pipelined-multiprocessor architecture with an energy-efficient approach to meet the requirement of processing of alignment operation at hardware speed. This architecture introduces register-file concept, instead of conventional memory-based approach, to reduce run-time storage requirement as well as power consumption. In addition, the proposed alignment architecture does not incur any preprocessing operations present in most of the existing alignment approaches. Moreover, it does not need any sorting or comparison operation during the preparation of final sequence alignment. This architecture achieves 128 GCUPS performance and also acquires 107.20 GCUPS/W throughput with respect to power consumption. The proposed architecture brings down 97.29% power consumption compared to state of the art multiprocessor architectures. Experimentally, it has been observed that, this novel architecture exhibits reduction in energy consumption by ≈97.51% and achieves 2.56 GCUPS gain factor in an energy-efficient manner over all existing hardware approaches.

Sequence alignments are currently gaining close attention due to their great impact on the quality aspects of life such as facilitating early disease diagnosis, identifying the characteristics of a newly discovered sequence, etc.. With the rapid growth of genomic data, searching for a sequence homology over huge databases is unable to produce results within a realistic time. Hence, it demands an efficient sequence alignment accelerator to improve the performance of the system. Though some popular acceleration platforms, like supercomputers, Very Large Scale Integration (VLSI) chip, Graphics Processing Unit (GPUs) and Field Programmable Gate Arrays (FPGAs) based devices are available, but they are unable to meet the intended requirement to the current growth of genome database. This paper presents a parallel dynamic approach for global pairwise alignment algorithm using GPU to handle such large database. The approach performs the alignment procedure in CUDA-enabled GPU platform by creating dynamic threads to perform parallel execution. This GPU-based implementation is tested using pseudorandom database and various length of sequences. The execution result shows reasonably better performance in terms of time and space requirement with respect to existing GPU-based optimal pairwise sequence alignment approaches.