This paper presents a single-ended four-level pulse amplitude modulation (PAM-4) receiver for memory interfaces. The front-end employs a T-coil, an inverter-based hybrid continuous-time linear equalizer (CTLE), and a decision-feedback equalizer (DFE) to compensate for complex channel losses. Additionally, a cross-coupled pair (XCP) is incorporated to enhance the single-to-differential (S2D) conversion performance of the CTLE, which results in improved differential-mode gain. Unlike conventional current-mode DFE implementations, the proposed DFE employs voltage-feedback using resistive digital-to-analog converters (DACs), source followers (SFs), and voltage multiplexers (VMUXes) to ensure robust operation. To verify the capability of the proposed single-ended PAM-4 receiver, a prototype is fabricated using 40-nm CMOS technology, occupying an active area of 0.039 mm${}^{\mathbf {2}}$. The 36 Gb/s single-ended PAM-4 receiver achieves a bit error rate (BER) below 10${}^{\mathbf {-12}}$over a channel exhibiting 11.71 dB insertion loss at 9 GHz. The receiver consumes 51.89 mW, achieving an energy efficiency of 1.44 pJ/bit.

This paper presents the process of generating the layout of the 8-bit Successive Approximation Register Analog to Digital Converter (SAR ADC). By utilizing LAYGO2 [1], a Python framework that allows for detailed and flexible specification of custom layout generation processes, code-based generators for the component blocks of a SAR ADC were developed according to their specific operational characteristics and requirements. As a result, 85.5% of the SAR ADC was automatically generated. The SAR ADC test chip was fabricated in a 14-nm CMOS FinFET process and achieved an SNDR of 41.67 dB at 500 MS/s, consuming 2.07 mW from 0.9 V supply, and occupying an area of 4,131 um2.

This paper presents a 56-Gb/s 3-tap feed-forward equalizer (FFE) four-level pulse-amplitude modulation (PAM-4) transmitter (TX) frontend for wireline applications. The proposed transmitter frontend operates at a 0.85-V termination voltage utilizing external surface-mounted (SMT) bias-tees. Unlike conventional tail-less current-mode logic (CML) drivers with variable gate biases, the transmitter frontend employs shunt-FFE for fewer variations in output common-mode levels. The design is fabricated in 40-nm CMOS technology and occupies 0.021 mm2. The proposed PAM-4 transmitter design operating at 56 Gb/s consumes 22.0 mW from 0.85-V supply voltage, achieving 0.39-pJ/bit energy efficiency.

A 96-Gb/s PAM-8 transmitter with a transition-boosted current-mode logic (TBCML) driver is introduced and fabricated in 40-nm CMOS technology. The proposed TBCML driver incorporates cross-coupled gate voltage boosting and feedforward coupling techniques to enhance transition speeds for high-speed operation. The implemented transmitter achieves a differential peak-to-peak output swing of 657 mV at a data rate of 96 Gb/s. Feedforward equalization (FFE) is applied to mitigate inter-symbol interference (ISI). The prototype transmitter occupies a die area of 0.15 mm2and achieves an energy efficiency of 4.33 pJ/b with a total power consumption of 416 mW.

This paper describes a variation-robust transceiver with four-tap feed-forward equalization (FFE) and real-time calibration techniques. The design adopts the common-mode balanced and robust FFE (CMBB-FFE), which improves the previous current-mode coefficient-error-robust FFE (B-FFE) to achieve the consistent common-mode level across data patterns and support voltage mode operation. The real-time receiver calibration method adjusts sampling threshold voltages and clock phases in the middle of normal link operation, to enhance the sampling margin under dynamic drifting conditions. The transceiver test chip is fabricated in a 28-nm CMOS process. It occupies 0.419 mm$^{\mathbf {2}}$, achieving 20 Gb/s with 9.82-pJ /bit energy efficiency and 33.3% wider horizontal eye-opening by adopting the CMBB-FFE and real-time calibration techniques.

A single-mode buck-boost converter that generates a 3.3-V power supply from a variable input voltage (${V} _{\mathbf {IN}}$) range of 2.7–4.2 V for mobile li-ion battery applications is presented. The proposed buck-boost converter employs a switched-capacitor-based buck-converter operation, in which the voltage switching operation is followed by an LC filter. This ensures continuous output current delivery and reduces conduction loss in the inductor. An efficient power-stage structure and its operation are introduced, wherein only one resistive component is connected in series with the inductor during all operation phases. The proposed buck-boost converter has been implemented in a 180-nm BCDMOS process and regulates an output voltage of 3.3 V from a${V} _{\mathbf {IN}}$range of 2.7–4.2 V by single-mode step-up/down operation. The peak efficiency of 93.4% is achieved at 2.7-V${V} _{\mathbf {IN}}$, and the peak efficiency above 90% is obtained over the entire${V} _{\mathbf {IN}}$range.

We present an LC-based hybrid sub-sampling phase-locked loop (PLL). A novel tri-state integral path is applied to reduce the loop filter (LF) area and eliminate ripples on the control signals. The effectiveness of the proposed technique is compared with type-II hybrid PLL and PLL using delta-sigma modulator. The 24.6-29.6GHz PLL instance implemented in 28-nm planar process achieves RMS jitter of 44fs and -254.8dB FOM and consumes power of 17mW from a 0.9/0.95V supply.

This paper presents a high-speed single-ended 4-level pulse amplitude modulation (PAM-4) transceiver for next-generation memory interfaces, achieving a data rate of 32Gb/s. The proposed asymmetrically terminated PAM-4 driver is optimized for pseudo open drain (POD) channel configurations and improves signal-to-noise ratio (SNR) with a larger output swing. The dynamic logic-based high-speed 4-to-1 serializer enhances the transmitter output’s jitter characteristic by avoiding high-frequency components in the selection signals. The 4-tap feed-forward equalizer (FFE) with two operation modes and one sliding tap flexibly compensates for inter-symbol interference (ISI) of the channel. In the receiver frontend, a continuous-time linear equalizer (CTLE), which utilizes a trans-admittance stage (TAS) and a trans-impedance amplifier (TIA) with an inductive load, provides high-frequency boosting and robust single-to-differential conversion performance through the design techniques of current source gain-boosting and capacitive compensation. The low kickback noise comparators mitigate clock feedthrough and noise coupling during multi-phase PAM-4 sampling and embed the 1-tap PAM-4 decision feedback equalizer (DFE) operation by directly feeding back the previous sampling phase’s outputs. The transceiver prototype fabricated in 28-nm CMOS technology occupies 0.126 mm2. At 32 Gb/s, a bit error rate of under$10^{-12}$was achieved with a 6.25% eye margin and an energy efficiency of 3.37 pJ/bit while equalizing the 6.87-dB channel loss at 8 GHz.

This article presents an automatic layout generation framework in advanced CMOS technologies. The framework extends the template-and-grid-based layout generation methodology to produce optimal layouts more efficiently. Layout templates and grids are dynamically created and adjusted during the generation phase to provide more reusability and flexibility. Virtual instances are used to encapsulate the dynamically generated layout structures. Internal node probes embedded in the dynamic templates capture parasitic effects precisely. The framework also implements various post-processing functions to handle process-specific tasks while maintaining the overall process portability of procedural layout generators. The post-processing functions include cut/dummy pattern generation and multiple-patterning adjustment. The generator description coverage is enhanced with circular grid indexing/slicing and conditional conversion operators. The layout generation framework is applied to generate various DRC/LVS clean layouts automatically in advanced CMOS technologies, achieving 0.66–249.35 transistors-per-line (the ratio of the generated transistor count to the source lines of code) generation efficiencies.

This article introduces a cascaded sliding-block decision feedback equalizer (SB-DFE) that equalizes multiple precursor and postcursor intersymbol interference (ISI). The paper also presents an enhanced statistical analysis for the DFE in the presence of residual ISI and additive white Gaussian noise (AWGN), along with generalized expressions for the probability and expected length of DFE burst errors. In addition, the statistical analysis is extended to the conventional SB-DFE and our proposed cascaded SB-DFE to accurately estimate their equalization capability, latency, and steady-state bit error rate (BER). The simulation results reveal that the cascaded SB-DFE provides as low BER as the mininum mean-squared error - DFE (MMSE-DFE) with substantially lower latency and hardware overhead.

In this paper, we introduce effective bus data en-coding schemes for next-generation interfaces of DRAM with an analysis of their energy and lane efficiency characteristics. The Pulse-Amplitude-Modulation-4 (PAM-4) signaling technique has recently been adopted to memory interfaces due to their increased per-pin data-rate requirements. However, as the power consumption profile of PAM-4 symbols differs from that of NRZ symbols, the conventional Dynamic Bus Inversion (DBI) encoding fails to achieve an expected reduction of termination power. Therefore, this paper proposes data encoding schemes applicable to the PAM-4 memory links and compares their performances in terms of the termination energy with experimental results. We evaluate the proposed approaches by applying data encoding to DRAM memory access traces obtained from executing benchmarks on ARM/x86 ISA-based processors, including caches, simulated on the gem5 architecture simulator. The experimental results show that our advanced encoding algorithms enable us to achieve doubled data rate with minimal power consumption overhead.

We present a ring-oscillator-based sub-sampling phase-locked loop (PLL) using a generator-based design flow. A hybrid loop with a delta-sigma ($\Delta \Sigma$) modulator is applied to reduce the loop filter (LF) area and the control ripple. The generator automatically produces the ring oscillator and PLL to meet the provided specifications. The 10-GHz PLL instance implemented in 28-nm planar process achieves RMS jitter of}299.5 fs and power of 9.9 mW from a 1-V supply.

This paper presents a 1.5-GS/s 6-bit single-channel loop-unrolled successive approximation register (SAR) analog-to-digital converter (ADC) using speculative capacitive DAC (CDAC) switching control technique. The proposed SAR ADC achieves a high sampling rate by eliminating additional delays in typical loop-unrolled SAR ADCs related to settling time constraints in their CDACs. Specifically, the CDACs are duplicated and controlled in speculative ways so that the CDAC outputs passage to their next values before completing the regeneration operation of comparators, thereby improving timing constraints for successive approximations. The switching power overhead from the CDAC speculation is mitigated by introducing an energy-efficient CDAC control technique that produces desired voltage transients with minimal power overheads. The prototype of the proposed SAR ADC is fabricated in a 28-nm CMOS technology and occupies an active area of 0.0038-mm2. The design consumes 5.8 mW from a 1.2-V supply. The ADC achieves 1.5-GS/s sampling frequency with a 31-dB SNDR at a low input frequency and a 28.6 dB at the Nyquist frequency without applying any offset calibration techniques, achieving the highest sampling frequency among the 6-bit single-channel loop-unrolled SAR ADCs reported.

This paper introduces a physical layout design methodology that produces DRC-clean, area-efficient, and programmable layouts of digital circuits in advanced DRAM processes. The proposed methodology automates the layout generation process to enhance design productivity, while still providing rich customization for efficient area and routing resource utilizations. Process-specific parameterized cells (PCells) are combined with process-independent place-and-route functions to automatically generate area-efficient and programmable layouts. Routing grids are optimized to enhance the area and routing efficiency. The proposed method reduced the design time of digital layouts by 80% compared to a manual design with high layout qualities, significantly enhancing the design productivity.

LAYout with Gridded Objects (LAYGO), a Python-based layout-generation engine for enhancing the design productivity of custom circuit layouts in advanced CMOS processes, is presented and verified by implementing a time-interleaved SAR (TI-SAR) ADC instance in a 16 nm CMOS FinFET technology. LAYGO supports rapid generation by placing customized templates on process-specific placement grids, thereby encapsulating the design rules and process-specific structures. The templates can be located based on their relative positional information, which further enhances the description capability and portability. Interconnecting wires are routed on the grids for design rule abstractions, with additional customizations and support for multi-patterning. The functions for the on-grid placement and routing use advanced indexing and slicing with multi-dimensional object containers to improve the description and parameterization capabilities. Multiple TI-SAR ADC layouts are generated using LAYGO in 28-16 nm CMOS technologies. One instance is fabricated in a 16 nm CMOS FinFET process and measured, achieving a 38.2 dB signal-to-noise-and-distortion ratio (SNDR) at 7 GS/s after digital calibration and consuming 45.2 mW. Owing to its high customization capability, the design achieved the highest sampling rate (7 GS/s) among the generated ADCs.

Raw data acquired by imaging devices are converted into digital images by post-processing algorithms. However, these algorithms are significantly affected by numerous illumination conditions. Particularly, in the case in which illumination conditions depend on canonical light sources, unwanted light sources that locally illuminate the scene or mixed light from several light sources are recognized as the spatially varying illumination conditions. These complex illumination conditions cause several artifacts by affecting the digital image acquisition process. For example, optical aberrations are generated by refraction of complex light, or illumination estimation is significantly affected by the different color temperatures of multiple light sources. To overcome these problems, this study proposes an algorithm that decomposes the complex illumination from several light sources. First, the spatially varying illumination condition is discussed, and the artifacts generated by the conditions, such as false colors and aberrations, are analyzed. Second, mixed light from several canonical light sources is decomposed based on the imaging devices and spectral information of the canonical light sources. The proposed method has low complexity and increased applicability. Furthermore, the improvement scheme based on the proposed method has a parallelized structure and can be easily applied to various types of algorithms, such as color constancy, deconvolution, denoising, and contrast enhancement. The algorithms employing the improvement scheme show the potential of the proposed method for solving the problems associated with multiple light sources.

Image deconvolution is an ill-posed problem that usually requires prior knowledge for regularizing the feasible solutions. In literature, iterative methods estimate an intrinsic image, minimizing a cost function regularized by specific prior information. However, it is difficult to directly minimize the constrained cost function, if a nondifferentiable regularization (e.g., the sparsity constraint) is employed. In this paper, we propose a nonderivative image deconvolution algorithm that solves the under-constrained problem (i.e., a non-blind image deconvolution) by successively solving the permuted subproblems. The subproblems, arranged in permuted sequences, directly minimize the nondifferentiable cost functions. Various Lp-regularized (0 < p ≤ 1, p = 2) objective functions are utilized to demonstrate the pixel-wise optimization, in which the projection operator generates simplified, low-dimensional subproblems for estimating each pixel. The subproblems, after projection, are dealt with in the corresponding hyperplanes containing the adjacent pixels of each image coordinate. Furthermore, successively solving the subproblems can accelerate the deconvolution process with a linear speed-up, by parallelizing the subproblem sequences. The image deconvolution results with various regularization functionals are presented and the linear speed-up is also demonstrated with a parallelized version of the proposed algorithm. Experimental results demonstrate that the proposed method outperforms the conventional methods in terms of the improved-signal-to-noise ratio and structural similarity index measure.