As silicon photonic integrated circuits (PICs) increase in complexity, ensuring their reliability against manufacturing and operational variations necessitates robust Design-for-Test (DfT) strategies. We present an adaptable methodology for DfT insertion in large-scale PICs, centered on physics-informed hypergraph partitioning. Our approach uniquely leverages hypergraph-based weighting derived from process sensitivities (e.g. etch, doping) and operational drifts (e.g. thermal, injection), quantified using partial derivatives from foundry data or Transfer Matrix Method (TMM) simulations. This assigns actionable risk values to both devices (nodes) and interconnects (hyperedges). We employ k-way partitioning to achieve finer sub-network isolation and targeted test access, crucial for vulnerability localization in complex PICs like multi-level ring resonator networks or large MZI-based crossbars. Experiments performed on PIC designs demonstrate the application of the proposed risk coverage metric to vulnerability localization and test point insertion, achieved with quantifiable and moderate overhead.