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Eshan Bhatia

dblp:177/5974 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 2019
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 91% Processor architecture and microarchitecture · 9%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems
cache
0.412019
Perceptron-based prefetch filtering · ISCA 2019
Memory systems › cache › prefetching
hardware prefetching
0.412019
Perceptron-based prefetch filtering · ISCA 2019
Memory systems › cache › prefetching
prefetch filtering
0.412019
Perceptron-based prefetch filtering · ISCA 2019

Methods — techniques the papers use, named apart from their topics

perceptron · 0.4
YearPublicationVenuePosition
2019 Perceptron-based prefetch filtering
abstract
Hardware prefetching is an effective technique for hiding cache miss latencies in modern processor designs. Prefetcher performance can be characterized by two main metrics that are generally at odds with one another: coverage, the fraction of baseline cache misses which the prefetcher brings into the cache; and accuracy, the fraction of prefetches which are ultimately used. An overly aggressive prefetcher may improve coverage at the cost of reduced accuracy. Thus, performance may be harmed by this over-aggressiveness because many resources are wasted, including cache capacity and bandwidth. An ideal prefetcher would have both high coverage and accuracy.
Eshan Bhatia, Gino Chacon, Seth H. Pugsley, Elvira Teran, Paul Gratz, Daniel A. Jiménez
ISCA1