EDBT 2026 Demo / reviewers in the wild / expert
Zikui Wei
dblp:177/6259
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 2016
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 59% Energy-efficient computing · 23% Integrated circuit design · 18% |
Topics — the 7 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems
cache |
0.2 | 1 | 2016 | cNV SRAM: CMOS Technology Compatible Non-Volatile SRAM Based Ultra-Low Leakage Energy Hybrid Memory System · IEEE Trans. Computers 2016 |
Energy-efficient computing
leakage power reduction |
0.2 | 1 | 2016 | cNV SRAM: CMOS Technology Compatible Non-Volatile SRAM Based Ultra-Low Leakage Energy Hybrid Memory System · IEEE Trans. Computers 2016 |
Integrated circuit design
low-power circuit design |
0.2 | 1 | 2016 | cNV SRAM: CMOS Technology Compatible Non-Volatile SRAM Based Ultra-Low Leakage Energy Hybrid Memory System · IEEE Trans. Computers 2016 |
Memory systems › non-volatile memory
non-volatile SRAM |
0.2 | 1 | 2016 | cNV SRAM: CMOS Technology Compatible Non-Volatile SRAM Based Ultra-Low Leakage Energy Hybrid Memory System · IEEE Trans. Computers 2016 |
Memory systems › random-access memory
SRAM |
0.2 | 1 | 2016 | cNV SRAM: CMOS Technology Compatible Non-Volatile SRAM Based Ultra-Low Leakage Energy Hybrid Memory System · IEEE Trans. Computers 2016 |
Energy-efficient computing
memory energy efficiency |
0.1 | 1 | 2016 | cNV SRAM: CMOS Technology Compatible Non-Volatile SRAM Based Ultra-Low Leakage Energy Hybrid Memory System · IEEE Trans. Computers 2016 |
Memory systems
on-chip memory |
0.1 | 1 | 2016 | cNV SRAM: CMOS Technology Compatible Non-Volatile SRAM Based Ultra-Low Leakage Energy Hybrid Memory System · IEEE Trans. Computers 2016 |
Methods — techniques the papers use, named apart from their topics
simulation · 0.2circuit-level design · 0.2architectural-level design · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2016 | cNV SRAM: CMOS Technology Compatible Non-Volatile SRAM Based Ultra-Low Leakage Energy Hybrid Memory SystemabstractA CMOS technology compatible non-volatile SRAM (cNV SRAM) is proposed in this paper to achieve energy efficient on-chip memory. cNV SRAM works as conventional 8T SRAM to keep high speed in work mode; in sleep mode, it backs up the data in its NV component and switches off the power supply, thereby minimizing the leakage energy without data loss. The circuit- and architectural- level implementation schemes of cNV SRAM are developed considering multiple key performance parameters including energy dissipation, access time, write time, noise margin, layout area, restoration time, and injection charges. Simulation results on SPEC 2000 benchmark suite demonstrate that cNV SRAM realizes 86 percent energy savings on average with negligible performance impact and small hardware overhead as compared to conventional SRAM. Finally, the impact of the sleep time and memory size on the effectiveness of cNV SRAM is analyzed in detail and it shows that cNV SRAM is particularly effective to implement large on-chip memories with long idle time. Haibin Yin, Zikui Wei, Zezhong Yang, Na Gong |
IEEE Trans. Computers | 4 |