The security closure of integrated circuits (ICs) is an emerging area of research within the very large scale integration (VLSI) community. Malicious third parties, referred to as “attackers,” can employ various techniques to leak, alter, or manipulate the logic of a circuit. When targeting a completed layout, their primary goal is often the insertion of hardware trojans. In this work, we present algorithms that strengthen placement solutions against hardware trojan attacks. While state-of-the-art methods rely on exhaustive placement algorithms, we propose a clustering-based placement approach that reduces the number of moved cells by up to 17%. Additionally, we introduce a cell movement heuristic aimed at preventing increases in wirelength. Our methods reduce vulnerable placement sites by up to 78% while maintaining minimal impact on design performance. Compared to other approaches, our solution decreases the amount of moved cells to an average of 8%, mitigating the impact on wirelength to an average of 0.5%.

Single Event Transient (SET) faults are more notable every day at Earth applications. Even considering FinFET technology, the effects are not negligible. A circuit-level evaluation of radiation effects must consider each internal node of the cells, input vectors, particle type, and pulse width derived from the particle collision to determine the sensibility of the circuit under evaluation. Moreover, circuit characterization is time-consuming, involving many electrical simulations to reach an appropriate precision, mainly considering together with the process variability effects. This work evaluates how process variability and gate mapping impacts the radiation robustness on circuits composed by multigate devices in 7 nm FinFET technology. Firstly, the NAND2 and NOR2 gates are evaluated at nominal conditions and considering the process variability impact on the radiation sensitivity. After that, three different topologies of the same circuit are analyzed, showing that even when considering process variability, the circuit's robustness is highly dependent on its output gates and that the most sensitive part of a circuit may vary given process variability. Results also show that the$\mathbf{LET}_{th}$value may vary by order of magnitude due to the work-function fluctuation of NMOS and PMOS devices.

The technology scaling has boosted the importance and gravity of radiation faults. Hardening techniques are required to ensure a high level of reliability, mainly to the harsh critical applications. Hardware redundancy remains the most adopted option to deal with fault tolerance, mostly the TMR technique. However, the weakness of this technique is the voter circuit. This paper investigates the robustness of nineteen majority voter designs in the presence of a SET. The analysis explores critical diffusion areas and LET threshold. The results show designs with 3X difference in the number of critical diffusion areas and 6X in the LET threshold.

The aggressive technology scaling has significantly affected the circuit reliability. Several techniques have been explored to mitigate the scaling effects and guarantee a satisfactory reliability level. In this context, estimating circuit reliability is crucial and a challenge that has not yet been overcome. For decades, traditional reliability estimation techniques have used fixed logic gates reliability values. Recently, methods demonstrate that using fixed gate reliability values compromises the accuracy of the analysis. This work evaluates the impact of the estimated logic gate susceptibility in the reliability of several benchmarks circuits mapped with different sets of logic gates. The obtained results show a discrepancy in the reliability of the same circuit. However, the change in the reliability behavior may be considered the main contribution of this work. The utilization of fixed reliability values for logic gates provides reliability values inversely proportional to the number of gates in the circuit. The used approach captures the logical characteristics of the gates. The same circuit mapped with basic gates presents a difference in MTBF of 20%, while the one mapped with a complex set of gates is bigger than 70%.

New design methodologies are needed to improve the circuit robustness to deal with technology scaling issues. Traditional fault-tolerant approaches present severe overheads. Alternative solutions based on partial fault tolerance and fault avoidance are considered a possible solution to the reliability problem. An accurate evaluation of circuit reliability is fundamental to allow a reliability-aware automated design flow, where the synthesis tool could rapidly cycle through several circuit configurations to assess the best option. Most of the circuit reliability estimation methods use logic gate information as the starting point. The difference in logic gates reliability is neglected. This work proposes models capable of analyzing logic gates susceptibility in different abstraction levels. Three methods are proposed based on transistor arrangement, stick diagram, and layout of the logic gates. A 45nm standard cell library is used to validate the proposed methods. The achieved results are used to analyze ISCAS'85 benchmark circuit reliability. The obtained Mean Time Between Failures (MTBF) shows a considerable reduction of almost 50% compared to the values from traditional fixed logic gate reliability.

The progressive downscaling of feature sizes increases the susceptibility to Single Event Effects in integrated circuits. As a manner to mitigate soft errors, solutions incur significant performance and area penalties, especially when a design with fault-tolerant structure is overprotected. Probabilistic methods such as Probabilistic Transfer Matrix and Signal Probability Reliability Multi-Pass are prone to multiple faults scenario to evaluate circuits reliability. However, it is necessary that the probabilistic matrices of the gates being accurate enough for this task. This paper proposes a method to evaluate gate failure rate considering faults in Layout-Level. This method can be used to enrich the probabilistic matrices creation taking into account the characteristics of the layout in order to evaluate gate reliability and the failure rate more precisely. Results show a reduction of 40% in the failure rate just choosing the best layout alternative for the same logic function.

The circuit reliability in nanometer technologies has become an important aspect of circuit design. Techniques to improve reliability usually increase project costs. To avoid overdesign, techniques to estimate circuit reliability are commonly used. These techniques usually explore probabilistic Matrices to compute the circuit reliability. The matrices used to represent logic functions are simplified do not taking into account the logic gate design. In this way, the main goal of this thesis is to propose a method capable of creating probabilistic matrices from logic gates layouts and then improve the accuracy of the reliability evaluation methods.