Linearity testing, including differential nonlinearity (DNL) and integral nonlinearity (INL), is of great significance to evaluate the performance of an analog-to-digital converter (ADC). However, highly linear signal generator and large amount of samples are two challenges in conventional histogram testing method. This paper proposes a segmentation nonlinear model with partial polynomial fitting to reduce the required samples, while the source nonlinearity removal scheme relaxes the precision requirement of signal generator. The influence of noise and source resolution are analyzed. Measurement results show that with a 12-bit digital-to-analog converter (DAC) and 393 216 samples, the 16-bit ADC INL and DNL can be measured with estimation errors less than 0.3 LSB.

This article presents a background calibration method for timing skew in time-interleaved (TI) analog-to-digital converters (ADCs). The proposed algorithm employs fast adaptive particle swarm optimization (FAPSO) to detect the timing skews in sub-channels and compensates them using second-order finite impulse response (FIR) differentiators. This approach enables simultaneous convergence of each channel and reduces the convergence time significantly. Hardware implementation of the proposed timing skew calibration is synthesized by field-programmable gate array (FPGA), and it consumes a total power of 7.3 mW. The effectiveness of the proposed FAPSO algorithm is verified through a commercial 12-bit 3.6-GS/s 4-channel TI-ADC. After applying FAPSO timing skew calibration, the signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are improved by 16.5 and 29.6 dB, respectively.

This brief presents a digital background calibration technique for timing skew in time-interleaved (TI) analog-to-digital converters (ADCs). It updates the calibration step adaptively based on the detection error. This results in large update step initially, and it reduces with the calibration cycle going on. More than two times convergence time is saved compared with the conventional fixed update step method. Besides, by extending the compensation to second-order, both calibration range and accuracy are improved. To demonstrate the effectiveness of the proposed timing skew calibration, extensive simulation and measurement results are provided. It shows that after timing skew calibration, the signal-to-noise and distortion ratio (SNDR) and spurious free dynamic range (SFDR) of a two-channel prototype TI ADC are improved by 8.2 and 14.9 dB, respectively.