Demo Data from EDBT 2026 / reviewers in the wild / expert
Sriskanda Shamasunder
dblp:177/8586
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 2016
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1Software engineering, systems software and programming languages · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Network and information security
1 paper |
Systems and software security · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Processor architecture and microarchitecture · 100% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Systems and software security
exploitation |
0.2 | 1 | 2016 | HIPStR: Heterogeneous-ISA Program State Relocation · ASPLOS 2016 |
Systems and software security
return-oriented programming defense |
0.2 | 1 | 2016 | HIPStR: Heterogeneous-ISA Program State Relocation · ASPLOS 2016 |
Processor architecture and microarchitecture › chip multiprocessor
heterogeneous chip multiprocessor |
0.2 | 1 | 2016 | HIPStR: Heterogeneous-ISA Program State Relocation · ASPLOS 2016 |
Processor architecture and microarchitecture › multiprocessor architecture
heterogeneous-ISA |
0.2 | 1 | 2016 | HIPStR: Heterogeneous-ISA Program State Relocation · ASPLOS 2016 |
Systems and software security › exploitation
code reuse attack |
0.1 | 1 | 2016 | HIPStR: Heterogeneous-ISA Program State Relocation · ASPLOS 2016 |
Methods — techniques the papers use, named apart from their topics
program state randomization · 0.5
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2016 | HIPStR: Heterogeneous-ISA Program State RelocationabstractHeterogeneous Chip Multiprocessors have been shown to provide significant performance and energy efficiency gains over homogeneous designs. Recent research has expanded the dimensions of heterogeneity to include diverse Instruction Set Architectures, called Heterogeneous-ISA Chip Multiprocessors. This work leverages such an architecture to realize substantial new security benefits, and in particular, to thwart Return-Oriented Programming. This paper proposes a novel security defense called HIPStR -- Heterogeneous-ISA Program State Relocation -- that performs dynamic randomization of run-time program state, both within and across ISAs. This technique outperforms the state-of-the-art just-in-time code reuse (JIT-ROP) defense by an average of 15.6%, while simultaneously providing greater security guarantees against classic return-into-libc, ROP, JOP, brute force, JIT-ROP, and several evasive variants. Ashish Venkat, Sriskanda Shamasunder, Hovav Shacham, Dean M. Tullsen |
ASPLOS | 2 |