LoRa backscatter achieves long-range communication at the cost of only tens of micro-watts of power when implemented in integrated circuits (ICs), which makes it a potential enabler for massive IoT. However, despite the above advantages, we find that the current tag design wastes approximately 72% of the chip functional area due to the use of large-size inductors in the impedance loads array. This inefficiency significantly increases the cost per chip during mass production. To address this die area issue, we propose OsTAG, a novel LoRa backscatter design that eliminates all inductors in the impedance loads array while maintaining the same quantization resolution. The key innovation lies in the creation of virtual impedance using oversampling. Realizing such design requires overcoming the technical challenges of mitigating approximation error and managing oversampling clock imperfections. To validate our design, we develop prototype and an IC, demonstrating promising results in terms of both performance and efficiency. OsTAG is expected to cost only 28% of the existing chip area while achieving comparable hundred-meter level communication range.

With the rapid growth of network bandwidth, increases in CPU cores on a single machine, and application API models demanding more short-lived connections, a scalable TCP stack is performance-critical. Although many clean-state designs have been proposed, production environments still call for a bottom-up parallel TCP stack design that is backward-compatible with existing applications.