Demo Data from EDBT 2026 / reviewers in the wild / expert
Moonsang Kwon
dblp:178/3189
· DBLP profile ↗
2ranked-venue papers
0as first author
0since 2021 · last 2016
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2Software engineering, systems software and programming languages · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Storage systems · 71% Memory systems · 23% Cloud and datacenter computing · 5% | |
| Databases, data mining, and information retrieval
1 paper |
Information retrieval · 100% |
Topics — the 7 heaviest of 8, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Information retrieval
filtering |
0.2 | 1 | 2016 | Biscuit: A Framework for Near-Data Processing of Big Data Workloads · ISCA 2016 |
Storage systems
computational storage |
0.2 | 1 | 2016 | Biscuit: A Framework for Near-Data Processing of Big Data Workloads · ISCA 2016 |
Storage systems › computational storage
in-storage computing |
0.2 | 1 | 2016 | Biscuit: A Framework for Near-Data Processing of Big Data Workloads · ISCA 2016 |
Storage systems › storage devices › storage media
mobile storage |
0.2 | 1 | 2016 | Design and implementation of a mobile storage leveraging the DRAM interface · HPCA 2016 |
Memory systems › processing-in-memory
near-data processing |
0.2 | 1 | 2016 | Biscuit: A Framework for Near-Data Processing of Big Data Workloads · ISCA 2016 |
Storage systems › flash and SSD
solid-state drive |
0.2 | 1 | 2016 | Biscuit: A Framework for Near-Data Processing of Big Data Workloads · ISCA 2016 |
Memory systems › memory controller
DRAM interface |
0.1 | 1 | 2016 | Design and implementation of a mobile storage leveraging the DRAM interface · HPCA 2016 |
Methods — techniques the papers use, named apart from their topics
dataflow programming · 0.5storage controller chip design · 0.2host software stack · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2016 | Design and implementation of a mobile storage leveraging the DRAM interfaceabstractStorage I/O performance remains a key factor that determines the overall user experience of a computer system. This is especially true for mobile systems as users commonly browse and navigate through many high-quality pictures and video clips stored in their device. The appetite for more appealing user interface has continuously pushed the mobile storage interface speed up; emerging UFS 2.0 standard provisions a maximum bandwidth of as high as 1,200 MB/s. In this work, we propose, design, and implement a mobile storage architecture that leverages the high-speed DRAM interface for communication, thus substantially expanding the storage performance headroom. In order to effectively turn the existing DRAM interface into a storage interface, we design a new storage protocol that runs on top of the DRAM interface. Our protocol builds on a small host interface buffer structure mapped to the system's memory space. Based on this protocol, we develop and fabricate a storage controller chip that natively supports the LPDDR3 interface. We also develop a host software stack (Linux device driver and boot loader) and a host platform board. Finally we show the feasibility of our proposal by constructing a full Android system running on the developed storage device and platform. Our detailed evaluation shows that the proposed storage architecture has very low protocol handling overheads and compares favorably to a UFS 2.0 device. The proposed architecture obviates the need for implementing a separate host-side storage controller on a mobile CPU chip. Sungyong Seo, Youngjin Cho, Youngkwang Yoo, Otae Bae, Jaegeun Park, Heehyun Nam, Sunmi Lee, Yongmyung Lee, Seungdo Chae, Moonsang Kwon, Jin-Hyeok Choi, Sangyeun Cho, Duckhyun Chang |
HPCA | 10 |
| 2016 | Biscuit: A Framework for Near-Data Processing of Big Data WorkloadsabstractData-intensive queries are common in business intelligence, data warehousing and analytics applications. Typically, processing a query involves full inspection of large in-storage data sets by CPUs. An intuitive way to speed up such queries is to reduce the volume of data transferred over the storage network to a host system. This can be achieved by filtering out extraneous data within the storage, motivating a form of near-data processing. This work presents Biscuit, a novel near-data processing framework designed for modern solid-state drives. It allows programmers to write a data-intensive application to run on the host system and the storage system in a distributed, yet seamless manner. In order to offer a high-level programming model, Biscuit builds on the concept of data flow. Data processing tasks communicate through typed and data-ordered ports. Biscuit does not distinguish tasks that run on the host system and the storage system. As the result, Biscuit has desirable traits like generality and expressiveness, while promoting code reuse and naturally exposing concurrency. We implement Biscuit on a host system that runs the Linux OS and a high-performance solid-state drive. We demonstrate the effectiveness of our approach and implementation with experimental results. When data filtering is done by hardware in the solid-state drive, the average speed-up obtained for the top five queries of TPC-H is over 15x. Boncheol Gu, Andre S. Yoon, Duck-Ho Bae, Insoon Jo, Jonghyun Yoon, Jeong-Uk Kang, Moonsang Kwon, Chanho Yoon, Sangyeun Cho, Duckhyun Chang |
ISCA | 8 |