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Rolland R. Hackbart

dblp:178/3997 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1971
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 50% Distributed systems · 25% Electronic design automation · 25%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › digital circuit design › sequential circuit design
asynchronous sequential circuits		 0.011971
The Avoidance and Elimination of Function Hazards in Asynchronous Sequential Circuits · IEEE Trans. Computers 1971
Integrated circuit design
digital circuit design		 0.011971
The Avoidance and Elimination of Function Hazards in Asynchronous Sequential Circuits · IEEE Trans. Computers 1971
Distributed systems
fault tolerance		 0.011971
The Avoidance and Elimination of Function Hazards in Asynchronous Sequential Circuits · IEEE Trans. Computers 1971
Electronic design automation › logic synthesis › asynchronous circuit synthesis
hazard elimination		 0.011971
The Avoidance and Elimination of Function Hazards in Asynchronous Sequential Circuits · IEEE Trans. Computers 1971

Methods — techniques the papers use, named apart from their topics

gate delay utilization · 0.0critical race suppression · 0.0
YearPublicationVenuePosition
1971 The Avoidance and Elimination of Function Hazards in Asynchronous Sequential Circuits
abstract
Armstrong et al.[1] have shown how critical races and function hazards can be suppressed in asynchronous sequential circuits by using gate delays to advantage rather than introducing explicit delay elements, if certain delay assumptions are satisfied. This paper shows that the same techniques may be used to design circuits which will respond reliably to simultaneous changes of several input variables.
Rolland R. Hackbart, Donald L. Dietmeyer
 IEEE Trans. Computers1