The synchronous procedure and the asynchronous procedure for the synthesis of a master-slave circuit are examined. It is shown that the synchronous procedure leads to a circuit operating in fundamental mode, while the asynchronous procedure can be performed by taking into account the synchronous flow table. In both cases the same circuit is obtained.

Traditionally, synchronous sequential circuits are considered controlled by input pulses, and asynchronous sequential circuits by input levels. The aim of this note is to study the general properties of a class of asynchronous circuits with some inputs that can be thought of as driven by "pulses." The synthesis process and the internal structure of these circuits, called pulse input asynchronous sequential circuits (PA circuits), are investigated, and they are compared with pulse input synchronous circuits and with level input asynchronous circuits. Procedures are described to transform any flow table describing a synchronous circuit into a flow table describing an equivalent PA circuit, and to realize any normal mode asynchronous circuit by a PA circuit. Specific techniques for PA circuit state reduction and PA circuit state assignment are described in other papers.

Methods to realize race-free asynchronous sequential circuits by using appropriate single transition time (STT) state assignments have been described in the literature. This paper deals with that restricted class of asynchronous circuits (called pulse-input asynchronous circuits) for which in every input sequence each input state liis always followed by a special input state lo≠li. A method is presented to realize any pulse-input asynchronous sequential circuit with p internal states by a universal race-free STT state assignment in 2Eovariables, where Eo=[log2n] and n≤p is the number of the elements in a defined subset of internal states.

TOPI is a special-purpose computer for the synthesis and analysis of Boolean functions. The algorithms executed by TOPI have been developed specifically for this computer and are an evolution of the iterative consensus method. They allow the determination and classification of the prime implicants of a given Boolean function, as well as the determination of a number of irredundant normal coverings. The computer capabilities are limited to single-output functions of a maximum of 15 variables, or to n-output functions of a maximum of 15-n variables.

In this paper the possibility of removing in synchronous sequential machines some of the delay elements which store the internal state is discussed. Theorems and methods are given for eliminating all removable delay elements from a given realization of a synchronous machine and for selecting the assignments leading to a realization which requires the least number of delay elements. It is shown how the existence of these assignments is related to the existence of a pair of partitions on the set of states of the given machine. The internal performance of the sequential networks in which at least one but not all delay elements are removed is studied, and a "hybrid operating mode" is defined. A reclassification of sequential machines in terms of the algebraic structure of machines which relates to the number of removable delay elements is proposed. Sequential machines are, therefore, divided in three categories: synchronous, hybrid, and asynchronous, and some problems of decomposition for the three types of machines are discussed.

Abstract—This paper deals with computer-aided design of digital systems and presents a formal method for designing a digital system via state tables. The steps of the design method can be summarized as follows: a) a system is described by a set of microprograms written in a "transfer language," b) the set of microprograms is translated into a set of flow tables by an algorithm, and c) the flow tables are converted into logical diagrams by synthesis procedures. The purpose of step a) is to aid the designer in describing the system; the result of step b) makes it possible to reduce the logical complexity of the system by using systematic techniques of the sequential network theory; and the result of step c) is a system of interconnected sequential networks, operating simultaneously which may include iterative asynchronous networks.

The feasibility of a large-scale microprogrammed computer and some variations and extensions of Wilkes' scheme are examined. A general scheme is discussed to improve flexibility and reduce the number of micro-orders through massive use of the conditions for the next micro-order. A variable-cycle timing system that permits the speed of a synchronized computer to approach that of an asynchronous one is presented. Problems and solutions of input-output operations including time sharing and multiprogramming, and some technical problems, are discussed in detail. A particular scheme of the arithmetic unit included in a micro-programmed control unit is presented.