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Gerald Jay Burnett

dblp:178/4009 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1971
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 67% Performance modeling and evaluation · 33%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems › memory architecture
interleaved memory		 0.011971
On the Performance of Interleaved Memories with Multiple-Word Bandwidths · IEEE Trans. Computers 1971
Memory systems
memory bandwidth		 0.011971
On the Performance of Interleaved Memories with Multiple-Word Bandwidths · IEEE Trans. Computers 1971
Performance modeling and evaluation › performance model construction
memory system performance modeling		 0.011971
On the Performance of Interleaved Memories with Multiple-Word Bandwidths · IEEE Trans. Computers 1971

Methods — techniques the papers use, named apart from their topics

analytical modeling · 0.0
YearPublicationVenuePosition
1971 On the Performance of Interleaved Memories with Multiple-Word Bandwidths
abstract
Past studies of the performance of interleaved memory systems are extended in this note by adopting a more general model. The model assumes a system of N memory modules, each of which is made up of b submodules. Successive memory addresses are assigned to sequential submodules, modulo Nb. For increased effective memory bandwidth a so-called conflict buffer of size L + 1 is assumed to exist for storing address conflicts.
Edward G. Coffman Jr., Gerald Jay Burnett, Robert A. Snowdon
 IEEE Trans. Computers2