EDBT 2026 Demo / reviewers in the wild / expert
LeRoy W. Bearnson
dblp:178/4026 · also L. W. Bearnson
· DBLP profile ↗
3ranked-venue papers
1as first author
0since 2021 · last 1971
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 89% Integrated circuit design · 11% |
Topics — the 7 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
hardware verification and test |
0.0 | 2 | 1971 | On the Design of Minimum Length Fault Tests for Combinational Circuits · IEEE Trans. Computers 1971 Analyzing Errors with the Boolean Difference · IEEE Trans. Computers 1968 |
Electronic design automation › hardware verification and test
fault testing |
0.0 | 1 | 1971 | On the Design of Minimum Length Fault Tests for Combinational Circuits · IEEE Trans. Computers 1971 |
Electronic design automation › hardware verification and test › test generation › fault test generation
stuck-at fault test generation |
0.0 | 1 | 1971 | On the Design of Minimum Length Fault Tests for Combinational Circuits · IEEE Trans. Computers 1971 |
Electronic design automation › hardware verification and test › test generation
boolean difference |
0.0 | 1 | 1968 | Analyzing Errors with the Boolean Difference · IEEE Trans. Computers 1968 |
Electronic design automation › hardware verification and test
fault analysis |
0.0 | 1 | 1968 | Analyzing Errors with the Boolean Difference · IEEE Trans. Computers 1968 |
Integrated circuit design › digital circuit design
combinational logic |
0.0 | 1 | 1971 | On the Design of Minimum Length Fault Tests for Combinational Circuits · IEEE Trans. Computers 1971 |
Integrated circuit design
digital circuit design |
0.0 | 1 | 1971 | On the Design of Minimum Length Fault Tests for Combinational Circuits · IEEE Trans. Computers 1971 |
Methods — techniques the papers use, named apart from their topics
boolean difference function · 0.0boolean difference · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1971 | On the Design of Minimum Length Fault Tests for Combinational CircuitsabstractTechniques for deriving the minimum length tests are developed for irredundant combinational circuits that contain single faults. The development is based on the Boolean difference function. The Boolean difference function is expanded to form two analytical expressions that can be used to calculate the tests for any stuck-at-zero and stuck-at-one fault within combinational circuits. LeRoy W. Bearnson, Chester C. Carroll |
IEEE Trans. Computers | 1 |
| 1969 | Correction to "Analyzing Errors with the Boolean Difference"1
Frederick F. Sellers Jr., Mu Yue Hsiao, LeRoy W. Bearnson |
IEEE Trans. Computers | 3 |
| 1968 | Analyzing Errors with the Boolean DifferenceabstractAbstract—The Boolean difference is defined. It is shown through example how the Boolean difference is used to analyze the effect of errors on the outputs of logic circuits. Examples are given of error detection problems, analysis of redundant logic, and the generation of diagnostic sequences. Frederick F. Sellers Jr., Mu Yue Hsiao, LeRoy W. Bearnson |
IEEE Trans. Computers | 3 |