An algorithm for generating the complete test set of each stuck-at-0 (s-a-0) and stuck-at-1 (s-a-1) single fault in a combinational logic circuit is presented. The algorithm has been programmed to handle large circuits and is based on some properties of Boolean differences that make the generation of the complete test set very efficient. This algorithm can be modified so that it can be programmed on computers with small storage space. The modified algorithm can efficiently generate a subset of the complete test set of each of the faults under consideration. Some discussion is given to provide some insight into the relationship among undetectable faults, tests for detectable single faults, and circuit redundancies. Some ideas on the construction of test sets for detecting multiple faults based on Boolean differences are presented.

It is known that any switching function can be written as a totally symmetric function with some of its variables being repetitive. In this note, the least upper bound for the number of variables of the transformed totally symmetric functions based on the partition on the set of variables induced by the partial symmetry of the given switching function is found, and a technique for obtaining a transformed totally symmetric function with the number of variables equal to the least upper bound is given.

An algorithm for identifying all redundant variables of switching functions and an algorithm for identifying their symmetries (total or partial) are presented. Both algorithms are straightforward and very efficient. These algorithms are based on manipulating the binary and decimal number representations of the minterms of the switching function under testing.