Demo Data from EDBT 2026 / reviewers in the wild / expert
Z. Shaham
dblp:178/4936
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 1972
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Processor architecture and microarchitecture · 87% Memory systems · 13% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Processor architecture and microarchitecture
arithmetic unit |
0.0 | 1 | 1972 | A Note on Division Algorithms Based on Multiplication · IEEE Trans. Computers 1972 |
Processor architecture and microarchitecture
division algorithm |
0.0 | 1 | 1972 | A Note on Division Algorithms Based on Multiplication · IEEE Trans. Computers 1972 |
Memory systems
lookup table |
0.0 | 1 | 1972 | A Note on Division Algorithms Based on Multiplication · IEEE Trans. Computers 1972 |
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1972 | A Note on Division Algorithms Based on MultiplicationabstractThe algorithm of division based on multiplication is well known [1]-[5]. It permits utilization of fast multiply hardware in the implementation of division. The algorithm defines an iterative process in which numerator and denominator are both multiplied by the same factor misuch that the denominator converges to 1 and the numerator to the quotient. Convergence can be speeded up by finding a good value for m0, the first multiplier, by means of table lookup. The first two bits of the denominator D are 0.1 (assuming a normalized denominator). The next n bits are used to enter the table, yielding m0and D1=m0*D, where D1has a bits of convergence and as shown in [6]. Z. Shaham, Z. Riesel |
IEEE Trans. Computers | 1 |