Demo Data from EDBT 2026 / reviewers in the wild / expert
Otakar A. Horna
dblp:178/4937
· DBLP profile ↗
5ranked-venue papers
5as first author
0since 2021 · last 1988
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 4 first-authorGraphics, computer vision, multimedia, augmented reality and games · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
4 papers |
Electronic design automation · 58% Integrated circuit design · 42% |
Topics — the 6 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design
digital circuit design |
0.0 | 1 | 1972 | Nonlinear Termination of Transmission Lines · IEEE Trans. Computers 1972 |
Electronic design automation › signal integrity
transmission line termination |
0.0 | 1 | 1972 | Nonlinear Termination of Transmission Lines · IEEE Trans. Computers 1972 |
Electronic design automation
logic synthesis |
0.0 | 2 | 1965 | A Geometric Synthesis Method of Three-Input Majority Logic Networks · IEEE Trans. Electron. Comput. 1965 Majority-Logic Synthesis · IEEE Trans. Electron. Comput. 1963 |
Electronic design automation › logic synthesis › threshold logic synthesis
majority-logic synthesis |
0.0 | 2 | 1965 | A Geometric Synthesis Method of Three-Input Majority Logic Networks · IEEE Trans. Electron. Comput. 1965 Majority-Logic Synthesis · IEEE Trans. Electron. Comput. 1963 |
Integrated circuit design
analog and mixed-signal circuits |
0.0 | 1 | 1965 | Figure of Merit of Electronic Switching Devices · IEEE Trans. Electron. Comput. 1965 |
Electronic design automation › logic synthesis
boolean function representation |
0.0 | 1 | 1965 | A Geometric Synthesis Method of Three-Input Majority Logic Networks · IEEE Trans. Electron. Comput. 1965 |
Methods — techniques the papers use, named apart from their topics
schottky diode · 0.0nonlinear resistance · 0.0superposition theorem · 0.0minimal majority expansions · 0.0majority logic · 0.0linear approximation · 0.0geometric synthesis · 0.0don't care conditions · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1988 | Stability of adaptive FIR filtersabstractSvoboda's matrix inversion algorithm is used to analyze the adaptive FIR (finite-impulse response) filter. To get stable response, conditions of convergence and solvability have to be met. They determine the maximum correction step of the adaptive loop, the lower bound of the norm of output signal vector and the statistical properties of the reference signal. Methods of signal decorrelation are discussed and the upper bounds of resolution of a digital filter are derived. The long-term instability caused by parasitic DC voltages in the correction loop is analyzed and stabilization methods are suggested.> Otakar A. Horna |
ICASSP | 1 |
| 1972 | Nonlinear Termination of Transmission LinesabstractThe technique of using nonlinear resistances to terminate interconnecting transmission lines has been designed and tested, and is recommended for use in very high-speed digital circuits. This technique can save power, simplify wiring, and eliminate the problem of ringing in branched networks. Line matching by nonlinear resistance is investigated theoretically, and the properties, possibilities, and limitations of this method are discussed. Schottky diodes are recommended for this purpose. Otakar A. Horna |
IEEE Trans. Computers | 1 |
| 1965 | A Geometric Synthesis Method of Three-Input Majority Logic NetworksabstractA simple methods is developed for the synthesis of any arbitrary logical network by three-input majority gates. The methods is based on a generalization of a geometric interpretation of Boolean functions and on the fundamental property of a 3M gate; if there are the same signals on two inputs (representing logical O or I), then the output of the gate is independent of the third input signal. This represents therefore a ``don't care'' condition. In the synthesis procedure all functions are represented by a direct n-cube diagram. For recognition of various topological forms (k-dimensional subcubes, s-multiple stars) graphical-mechanical aids (contact and directional grids) can be used. The method of reduction of arguments after each synthesis step is shown and minimal majority expansions of all types of two and three-argument functions are tabulated. The problem of the time delay and/or ``symmetry in time'' in 3M-gate networks is treated in some detail. Otakar A. Horna |
IEEE Trans. Electron. Comput. | 1 |
| 1965 | Figure of Merit of Electronic Switching DevicesabstractTo specify the amplifying properties of various active electronic devices the gain-bandwidth product GNB is commonly used. The aim of this paper is to show that for active electronic (not electromagnetic) devices working in switching circuits, another figure of merit (analogous to the reciprocal of the gain-bandwidth product) could be derived from a simple model of an electronic switch. Otakar A. Horna |
IEEE Trans. Electron. Comput. | 1 |
| 1963 | Majority-Logic Synthesis
Otakar A. Horna |
IEEE Trans. Electron. Comput. | 1 |