A deductive method of fault simulation is described, which "deduces" the faults defected by a test at the same time that it simulates explicitly only the good behavior of logic circuit. For large logic circuits (at least several thousand gates) it is expected to be faster than "parallel" fault simulators, but uses much more computer memory than do parallel simulators.

This paper considers the general problem of the synthesis of asynchronous combinational and sequential circuits based on the assumption that gate delays may be unbounded and that line delays are suitably constrained. Certain problems inherent to circuit realizations with unbounded gate delays are discussed and methods of solving them are proposed. Specific synthesis techniques are presented for both combinational and sequential circuits. The use of completion detection necessitated by the assumption of unbounded gate delays also causes the circuits to stop operating for approximately half of all possible single faults, thus achieving a degree of self-checking.

Abstract—In an earlier paper, Unger showed that any normal mode flow table can be realized by an asynchronous sequential circuit without inserted delays in the feedback paths if and only if the flow table contains no essential hazards. No restrictions were placed on the relative magnitudes of line and gate delays. In this paper, we show that if the line delays are less than the minimum gate delay in the circuit, any normal mode sequential function can be realized without inserted delays. It is also shown that a weaker line delay assumption is sufficient. Two procedures for realizing asynchronous sequential circuits without inserted delays are presented.

A procedure is described for finding, by shortcut methods, a near-minimal set of tests for detecting all single faults in a combinational logic net. The procedure should prove useful for nets which are too large to be treated by more exact methods [2]. The set of tests so found also appears useful for diagnosing (i.e., locating) faults. The class of faults considered is that which causes connections to be stuck at logical one or logical zero. The nets considered may include AND, OR, NAND, NOR, and NOT gates. The bases of the procedure are the ``path sensitizing'' concept, and reduction of a net to its ``equivalent normal form,'' abbreviated enf. It is shown that if a set of tests can be found which detects an appropriate subset of faults in the enf, this set will detect all faults in the original net. The enf also provides a vehicle for systematically finding the most desirable tests, namely those which each detect many faults in the net. The procedure is illustrated in detail by an example.

A relatively fast procedure for assigning codes to the internal states of a sequential machine is described, which leads to a reasonably economical logical realization of the machine in many cases. The method is applicable to both completely and incompletely specified state tables, and permits the use of redundant internal variables if desired. An algorithm which implements the method approximately, and which is nonenumerative, has been programmed for the 7090 computer. The program handles problems with up to 100 internal states and 30 input symbols, or 3000 total states. It has performed a problem of maximum size in 120 seconds. Although fast, the method sometimes fails to attain truly economical logic in cases where unusually simple realizations are known to exist (e.g., the shift register). More comprehensive methods are now known, which in principle can produce better results, but which will be far more tedious to execute. They will be reported separately.

A set of procedures for assigning codes to internal states of a synchronous sequential machine so as to minimize the internal logic in two-level form is proposed. The procedures are based on interpreting the state table of a sequential machine as a set of mappings from present states into next states, under control of the inputs. Attention is focused on a particular subset of these mappings, called pr mappings. A numerical score is assigned to each pr mapping, which is a measure of the desirability of ``selecting'' the mapping for inclusion in a ``basic set'' of mappings. A basic set has the property of determining a unique code assignment (within a symmetry of the cube of internal states). The procedures are applied to a 3-stage shift register and result in the optimum encoding for that device. Finally, it is briefly indicated how three previous assignment methods, including one developed by the author, are related to those described here. Algorithms are presented for some but not all of the proposed procedures. These algorithms must be completed before the proposals can be implemented by a computer program.

Two techniques are described for designing multiapertured magnetic structures capable of realizing any specific logic function. The structures are made from rectangular hysteresis loop material. The designs are derived from the corresponding relay contact network by replacing each current carrying conductor in the relay circuit with its analog in the magnetic circuit, a flux-carrying conductor, replacing the emf with a pulsed mmf; and replacing each back contact with a saturable portion of the magnetic circuit in the topological equivalent of the contact network. A flux reversal through a saturated portion may then be blocked by means of an inhibiting Current applied to a suitable winding, the current representing a logical input variable. Thus flux may be ``steered'' through the magnetic circuit in a manner analogous to the steering of current through the contact network. For planar structures the first technique may be used to obtain the analog of series-parallel and bridge type circuits; parallel circuits. It is pointed out that the analog of a relay tree can be used as a standard structure suitable for realizing any Boolean function. Representative examples of both designs are shown, and experimental data are given.