Demo Data from EDBT 2026 / reviewers in the wild / expert
Jim Quinlan
dblp:178/5724
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1992
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1Software engineering, systems software and programming languages · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 100% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems › memory hierarchy
cache hierarchy |
0.0 | 1 | 1992 | Revisit the case for direct-mapped chaches: a case for two-way set-associative level-two caches · ISCA 1992 |
Memory systems › cache › cache organization
direct-mapped cache |
0.0 | 1 | 1992 | Revisit the case for direct-mapped chaches: a case for two-way set-associative level-two caches · ISCA 1992 |
Memory systems › cache › cache organization
set-associative cache |
0.0 | 1 | 1992 | Revisit the case for direct-mapped chaches: a case for two-way set-associative level-two caches · ISCA 1992 |
Memory systems › memory hierarchy › cache hierarchy
two-level cache |
0.0 | 1 | 1992 | Revisit the case for direct-mapped chaches: a case for two-way set-associative level-two caches · ISCA 1992 |
Memory systems
cache design |
0.0 | 1 | 1992 | Revisit the case for direct-mapped chaches: a case for two-way set-associative level-two caches · ISCA 1992 |
Methods — techniques the papers use, named apart from their topics
simulation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1992 | Revisit the case for direct-mapped chaches: a case for two-way set-associative level-two cachesabstractIn this paper we argue that a two-way second-level cache is a better design choice than a direct-mapped organization. We show two-way caches are as simple to implement as direct-mapped caches. If the cache controller contains tags, the data array can be organized as a single bank of standard SRAM. Otherwise, both tags and data can be organized as a single SRAM bank. Our simulation results show these novel two-way organizations outperform the direct-mapped approach. Wen-Hann Wang, Jim Quinlan, Konrad Lai |
ISCA | 2 |