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Calvin K. Tang

dblp:178/6081 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1970
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 88% Integrated circuit design · 12%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
logic synthesis
0.011970
Universal Logic Modules and Their Applications · IEEE Trans. Computers 1970
Electronic design automation › logic synthesis › logic network design
universal logic modules
0.011970
Universal Logic Modules and Their Applications · IEEE Trans. Computers 1970
Integrated circuit design
digital circuit design
0.011970
Universal Logic Modules and Their Applications · IEEE Trans. Computers 1970
Electronic design automation › logic synthesis › boolean function realization
symmetric function synthesis
0.011970
Universal Logic Modules and Their Applications · IEEE Trans. Computers 1970

Methods — techniques the papers use, named apart from their topics

boolean function decomposition · 0.0
YearPublicationVenuePosition
1970 Universal Logic Modules and Their Applications
abstract
Recent advances in integrated circuit technology and its potential advantage in logical design have motivated the search for modular synthesis techniques for logic networks. This problem may be divided into two parts: find appropriate modules; and develop efficient synthesis techniques for logic networks using a minimum number of modules. In this paper a new type of universal logic modules (ULM's) called the Q-type is presented. The Q-type ULM's are superior to the existing ULM's in the sense that they require fewer input/output terminals when n≥6 where n is the number of input variables of the ULM. Various techniques for synthesizing a logic network with a small number of ULM's are discussed. A much simpler type of modules, which is suitable to realize any symmetric or partially symmetric function and can be used as auxiliary building blocks for realizing any given logic function, is presented. A special kind of ULM's, called serially controlled ULM's which has only n+ 3 input/ output terminals, is also presented. For a ULM of this kind the signals for specifying the logic function to be realized are serially applied to one of its input terminals.
Stephen S. Yau, Calvin K. Tang
IEEE Trans. Computers2