EDBT 2026 Demo / reviewers in the wild / expert
Vinod Batra
dblp:178/6082
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 1970
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Integrated circuit design · 100% | |
| Theoretical computer science
1 paper |
Logic in computer science · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design
asynchronous circuit design |
0.0 | 1 | 1970 | Design of Asynchronous Unit Delays · IEEE Trans. Computers 1970 |
Integrated circuit design
digital circuit design |
0.0 | 1 | 1970 | Design of Asynchronous Unit Delays · IEEE Trans. Computers 1970 |
Logic in computer science
sequential circuit theory |
0.0 | 1 | 1970 | Design of Asynchronous Unit Delays · IEEE Trans. Computers 1970 |
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1970 | Design of Asynchronous Unit DelaysabstractAn asynchronous unit delay is an n-input n-output asynchronous sequential circuit such that the present value of the output n-tuple is equal to the value of the input n-tuple prior to the last input change. The delay is of significance as a building block for shift register realizations of asynchronous circuits. Vinod Batra |
IEEE Trans. Computers | 1 |