Demo Data from EDBT 2026 / reviewers in the wild / expert
Héctor Arango
dblp:178/6088
· DBLP profile ↗
8ranked-venue papers
3as first author
0since 2021 · last 1970
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 8 · 3 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
7 papers |
Electronic design automation · 58% Integrated circuit design · 28% Processor architecture and microarchitecture · 9% | |
| Theoretical computer science
2 papers |
Logic in computer science · 100% |
Topics — the 13 heaviest of 15, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
logic synthesis |
0.0 | 3 | 1970 | A Cyclic Algebra for the Synthesis of Ternary Digital Systems · IEEE Trans. Computers 1970 A Graphic Method for the Synthesis of Threshold Ternary Functions · IEEE Trans. Computers 1970 Threshold Synthesis of Ternary Digital Systems · IEEE Trans. Electron. Comput. 1966 |
Electronic design automation › logic synthesis
threshold logic synthesis |
0.0 | 2 | 1970 | A Graphic Method for the Synthesis of Threshold Ternary Functions · IEEE Trans. Computers 1970 Threshold Synthesis of Ternary Digital Systems · IEEE Trans. Electron. Comput. 1966 |
Electronic design automation › logic synthesis › multiple-valued logic synthesis
ternary threshold function |
0.0 | 1 | 1970 | A Graphic Method for the Synthesis of Threshold Ternary Functions · IEEE Trans. Computers 1970 |
Integrated circuit design
digital circuit design |
0.0 | 3 | 1966 | Base 3 vs Base 2 Synchronous Arithmetic Units · IEEE Trans. Electron. Comput. 1964 Threshold Synthesis of Ternary Digital Systems · IEEE Trans. Electron. Comput. 1966 A Ternary Storage Element Using a Conventional Ferrite Core · IEEE Trans. Electron. Comput. 1965 |
Logic in computer science › algebraic logic › boolean algebra › boolean function representation
functional decomposition |
0.0 | 1 | 1968 | Ternary Cyclo-Decompositions · IEEE Trans. Computers 1968 |
Integrated circuit design › digital circuit design
arithmetic circuit design |
0.0 | 1 | 1966 | A Fast Carry-Propagation Circuit for Base 3 Signed Non redundant Arithmetic · IEEE Trans. Electron. Comput. 1966 |
Processor architecture and microarchitecture
arithmetic unit |
0.0 | 1 | 1964 | Base 3 vs Base 2 Synchronous Arithmetic Units · IEEE Trans. Electron. Comput. 1964 |
Electronic design automation › logic synthesis
logic minimization |
0.0 | 1 | 1966 | Threshold Synthesis of Ternary Digital Systems · IEEE Trans. Electron. Comput. 1966 |
Memory systems
magnetic core memory |
0.0 | 1 | 1965 | A Ternary Storage Element Using a Conventional Ferrite Core · IEEE Trans. Electron. Comput. 1965 |
Processor architecture and microarchitecture › computer arithmetic
ternary arithmetic |
0.0 | 1 | 1964 | Base 3 vs Base 2 Synchronous Arithmetic Units · IEEE Trans. Electron. Comput. 1964 |
Integrated circuit design › digital circuit design › sequential circuit design
synchronous circuit |
0.0 | 1 | 1964 | Base 3 vs Base 2 Synchronous Arithmetic Units · IEEE Trans. Electron. Comput. 1964 |
Integrated circuit design › digital circuit design › arithmetic circuit design › adder design
ternary adder |
0.0 | 1 | 1966 | Threshold Synthesis of Ternary Digital Systems · IEEE Trans. Electron. Comput. 1966 |
Logic in computer science › algebraic logic
post algebras |
0.0 | 1 | 1970 | A Cyclic Algebra for the Synthesis of Ternary Digital Systems · IEEE Trans. Computers 1970 |
Methods — techniques the papers use, named apart from their topics
trial and error · 0.0threshold algebra · 0.0tabular procedure · 0.0midterms · 0.0hanson method · 0.0cyclization operation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1970 | A Graphic Method for the Synthesis of Threshold Ternary FunctionsabstractIn the final form of the Hanson method for the synthesis of ternary threshold functions on r-basis, a weighting vector appears whose coordinates were calculated by a tabular procedure. This must follow a definite ordered sequence since the value of each coordinate depends on the values of some of the previously calculated coordinates. Héctor Arango |
IEEE Trans. Computers | 2 |
| 1970 | A Cyclic Algebra for the Synthesis of Ternary Digital SystemsabstractThe original multivalued algebra defined by Post in 1921 [1] included the cyclization operation in its generating set. Up to now the algebra has not been used for the synthesis of ternary digital systems because of two shortcomings: no simple canonical forms are possible, and the cyclization is difficult to implement. Héctor Arango, Manuel Pascual, G. Roing |
IEEE Trans. Computers | 2 |
| 1968 | Ternary Cyclo-DecompositionsabstractAbstract—This note discusses a particular kind of ternary functional decomposition based on a ternary function ↑ to be performed on the set of composite functions. Such function is closely related to the cycling concept of Postian algebras. A systematic method is given to determine the set of all decompositions of that kind admitted by the function. Such set is called the cyclo-set and it is proved that it is a filter in the partitions lattice. Since any partition of the lattice can be expressed as an intersection of cardinality-2 partitions, it follows that the method consists merely in finding the infimum of the cardinality-2 partitions belonging to the cyclo-set and then determining the filter having this infimum as vertex. The existence of proper subsets of the cardinality-2 partitions set leading to the determination of the ifiter-vertex is discussed, and results obtained for functions of domain-order up to seven are stated. Finally, the total number of cyclo-decompositions for a given partitional structure is calculated. Héctor Arango, Alicia Chacur |
IEEE Trans. Computers | 1 |
| 1966 | Threshold implementation of ternary systems
Héctor Arango, Manuel Pascual, Max E. Valentinuzzi |
IEEE Trans. Electron. Comput. | 1 |
| 1966 | A Fast Carry-Propagation Circuit for Base 3 Signed Non redundant Arithmetic
Héctor Arango |
IEEE Trans. Electron. Comput. | 1 |
| 1966 | Threshold Synthesis of Ternary Digital SystemsabstractThis paper presents a synthesis method of ternary digital systems by means of a threshold algebra. The method is based on the fact that the K operations of any ternary function can be expressed as threshold operations on a set of functions called midterms. Such midterms can be easily generated from the outputs of the ternary multivibrators described by the authors in a previous paper [4]. The Quine method is extended to the minimization of ternary threshold normal forms. RTL circuits implementing the operations are described, and the threshold design of a fast carry propagation ternary adder is outlined in order to illustrate the method. Héctor Arango, Francisco Lorenzo |
IEEE Trans. Electron. Comput. | 2 |
| 1965 | A Ternary Storage Element Using a Conventional Ferrite CoreabstractA new group of time-delay polynomial approximations are obtained by trial and error methods. The results of the trial and error procedure suggest an analytic method for finding the new approximations. The new approximations and their usable bandwidths are tabulated for second-through sixth-order polynomials. Delay vs. frequency graphs of the fourth-and fifth-order polynomials are compared with several previously published approximations. Héctor Arango, Manuel Pascual |
IEEE Trans. Electron. Comput. | 2 |
| 1964 | Base 3 vs Base 2 Synchronous Arithmetic Units
Héctor Arango |
IEEE Trans. Electron. Comput. | 2 |