An efficient partitioning scheme based on current capability of MOS MSI technology was evolved in which four functional building blocks were defined for implementing computer digital architecture. The partitioning employs a bit slice concept to define registers and a universal logic gate for general two-or three-variable logic. A look-ahead carry for fast arithmetic and a heavily buffered OR gate structure for the control section complete the partitioning elements. Microsequencing for instruction decoding is accomplished with a state graph implemented with register FBB flip-flops.