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K. K. Chakrabarti

dblp:178/6125 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1970
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
logic synthesis		 0.011970
Complementary Function Approach to the Synthesis of Three-Level NAND Network · IEEE Trans. Computers 1970
Electronic design automation › logic synthesis
multilevel logic synthesis		 0.011970
Complementary Function Approach to the Synthesis of Three-Level NAND Network · IEEE Trans. Computers 1970
Electronic design automation › logic synthesis › two-level logic minimization
prime implicant		 0.011970
Complementary Function Approach to the Synthesis of Three-Level NAND Network · IEEE Trans. Computers 1970

Methods — techniques the papers use, named apart from their topics

cover and closure table · 0.0complementary function approach · 0.0
YearPublicationVenuePosition
1970 Complementary Function Approach to the Synthesis of Three-Level NAND Network
abstract
In the present paper efforts have been made to arrive at the three-level NAND network of any general Boolean function by utilizing its complementary function. It has been shown that the knowledge of the complementing gates of the three-level NAND circuit with minimum number of gates in the AND level can readily be obtained from the study of the prime implicants of the complementary function. A reduced form of the Cover and Closure (CC) table is suggested which is applicable in the above three-level NAND network synthesis. The paper also deals with the recognition of the class of functions for which the use of the CC table may be avoided to obtain the same network.
K. K. Chakrabarti, Arun K. Choudhury, M. S. Basu
 IEEE Trans. Computers1