EDBT 2026 Demo / reviewers in the wild / expert
Bernhard Feldman
dblp:178/9172
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1968
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 50% Integrated circuit design · 50% |
Topics — the 2 heaviest of 2, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design
digital circuit design |
0.0 | 1 | 1968 | High-Speed Fixed Memories Using Large-Scale Integrated Resistor Matrices · IEEE Trans. Computers 1968 |
Memory systems › non-volatile memory
read-only memory |
0.0 | 1 | 1968 | High-Speed Fixed Memories Using Large-Scale Integrated Resistor Matrices · IEEE Trans. Computers 1968 |
Methods — techniques the papers use, named apart from their topics
resistive linear coupling · 0.0large-scale integration · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1968 | High-Speed Fixed Memories Using Large-Scale Integrated Resistor MatricesabstractAbstract—A new READ-only memory design using resistive linear coupling has been developed for high-speed operation. Cost, reliability, and high-speed considerations lead to the use of large-scale integrated resistor matrices. Principles of operation, signal-to-noise ratios, circuits, and memory organization are discussed. The design and fabrication of large-scale integrated resistor matrices is emphasized. Cycle times as fast as 50 and 100 ns have been achieved on 256-word 80-bit modules. Charles A. David, Bernhard Feldman |
IEEE Trans. Computers | 2 |