Demo Data from EDBT 2026 / reviewers in the wild / expert
Maso Kato
dblp:178/9222
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1968
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Processor architecture and microarchitecture · 33% Parallel and multicore computing · 33% Reconfigurable computing and FPGAs · 33% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Parallel and multicore computing
parallel architecture |
0.0 | 1 | 1968 | The ILLIAC IV Computer · IEEE Trans. Computers 1968 |
Reconfigurable computing and FPGAs › coarse-grained reconfigurable architecture
processing element array |
0.0 | 1 | 1968 | The ILLIAC IV Computer · IEEE Trans. Computers 1968 |
Processor architecture and microarchitecture
SIMD |
0.0 | 1 | 1968 | The ILLIAC IV Computer · IEEE Trans. Computers 1968 |
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1968 | The ILLIAC IV ComputerabstractAbstract—The structure of ILLIAC IV, a parallel-array computer containing 256 processing elements, is described. Special features include multiarray processing, multiprecision arithmetic, and fast data-routing interconnections. Individual processing elements execute 4×106instructions per second to yield an effective rate of 109 operations per second. George H. Barnes, Richard M. Brown, Maso Kato, David J. Kuck, Daniel L. Slotnick, Richard A. Stokes |
IEEE Trans. Computers | 3 |