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Charles H. Thomas

dblp:178/9231 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1968
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Performance modeling and evaluation · 33% Electronic design automation · 33% Integrated circuit design · 33%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › analog and mixed-signal circuits
analog circuit design
0.011968
Transport Time-Delay Simulation for Transmission Line Representation · IEEE Trans. Computers 1968
Performance modeling and evaluation
simulation
0.011968
Transport Time-Delay Simulation for Transmission Line Representation · IEEE Trans. Computers 1968
Electronic design automation › circuit simulation
transmission line simulation
0.011968
Transport Time-Delay Simulation for Transmission Line Representation · IEEE Trans. Computers 1968

Methods — techniques the papers use, named apart from their topics

transport time-delay simulation · 0.0analog computer · 0.0
YearPublicationVenuePosition
1968 Transport Time-Delay Simulation for Transmission Line Representation
abstract
Abstract—Two practical methods for obtaining a pure transport time delay are described which are well suited for analog computer applications. Examples of transmission line simulations are given where traveling wave phenomena are of interest. An alternate approximare method of transmission line representation is derived utilizing the natural frequencies of the primitive line and requiring only standard computer components.
Charles H. Thomas
IEEE Trans. Computers1