Demo Data from EDBT 2026 / reviewers in the wild / expert
J. R. Anderson
dblp:178/9352
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 1953
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 77% Integrated circuit design · 23% |
Topics — the 2 heaviest of 2, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems
delay-line memory |
0.0 | 1 | 1953 | Electrical delay lines for digital computer applications · Trans. I R E Prof. Group Electron. Comput. 1953 |
Integrated circuit design
digital circuit design |
0.0 | 1 | 1953 | Electrical delay lines for digital computer applications · Trans. I R E Prof. Group Electron. Comput. 1953 |
Methods — techniques the papers use, named apart from their topics
pulse transmission analysis · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1953 | Electrical delay lines for digital computer applicationsabstractA survey of existing lumped parameter and distributed parameter delay lines has shown that their maximum. storage capacity is about 23 pulses and 15 pulses respectively regardless of total delay time. An analysis of pulse transmission through distributed delay lines indicates that dissipation in the inductive elements is the chief factor limiting storage capacity. A method is proposed for decreasing this dissipation through the use of high-Q nickel zinc ferrites around straight conductors for inductive elements. J. R. Anderson |
Trans. I R E Prof. Group Electron. Comput. | 1 |